| No. | parte # | Fabricante | Descripción | Hoja de Datos |
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Austin Semiconductor |
16 Meg x 16 SDRAM Synchronous DRAM Memory • Full Military temp (-55°C to 125°C) processing available • Configuration: 16 Meg x 16 (4 Meg x 16 x 4 banks) • Fully synchronous; all signals registered on positive edge of system clock • Internal pipelined operation; column address can be changed |
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Austin Semiconductor |
1M x 1 DRAM |
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Austin Semiconductor |
4 MEG x 16 DRAM • Single +3.3V ±0.3V power supply. • Industry-standard x16 pinout, timing, functions, and package. • 12 row, 10 column addresses • High-performance CMOS silicon-gate process • All inputs, outputs and clocks are LVTTL-compatible • Extended Data-Out (E |
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Austin Semiconductor |
256K x 1 DRAM |
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Austin Semiconductor |
256K x 1 DRAM |
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Austin Semiconductor |
4 Meg x 16 SDRAM Synchronous DRAM Memory • • • • • • • • • • • • • www.DataSheet4U.com AS4SD4M16 PIN ASSIGNMENT (Top View) 54-Pin TSOP Extended Testing Over -55°C to +125° C and Industrial Temp -40°C to 85° C WRITE Recovery ( tWR/ tDPL) tWR = 2 CLK Fully synchronous; all signals registere |
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Austin Semiconductor |
32Mx72 DDR2 SDRAM iNTEGRATED Plastic Encapsulated Microcircuit DDR2 Data rate = 667, 533, 400 Available in Industrial, Enhanced and Extended Temp Package: • 255 Plastic Ball Grid Array (PBGA), 25 x 32mm • 1.27mm pitch Differential data strobe (DQS, DQS#) per byte Internal, pip |
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Austin Semiconductor |
8 Meg x 16 x 4 Banks Double Data Rate SDRAM COTS • VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V • Bidirectional data strobe (DQS) transmitted/received with data, i.e., source-synchronous data capture (has two – one per byte) • Internal, pipelined double-data-rate (DDR) architecture; two data accesses per |
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Austin Semiconductor |
512Mb: 32 Meg x 16 SDRAM • Full Military temp (-55°C to 125°C) processing available • Configuration: 32 Meg x 16 (8 Meg x 16 x 4 banks) • Fully synchronous; all signals registered on positive edge of system clock • Internal pipelined operation; column address can be changed |
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Austin Semiconductor |
512K x 32 x 4 Banks (64-Mb) Synchronous SDRAM • Full Military temp (-55°C to 125°C) processing available • Configuration: 512K x 32 x 4 banks • Fully synchronous; all signals registered on positive edge of system clock • Internal pipelined operation; column address can be changed every clock cyc |
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Austin Semiconductor |
256K x 4 DRAM |
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Austin Semiconductor |
32Mx64 DDR2 SDRAM iNTEGRATED Plastic Encapsulated Microcircuit DDR2 Data rate = 667, 533, 400 Available in Industrial, Enhanced and Military Temp Package: • 255 Plastic Ball Grid Array (PBGA), 25 x 32mm • 1.27mm pitch Differential data strobe (DQS, DQS#) per byte Internal, pip |
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Austin Semiconductor |
64Mx64 DDR2 SDRAM w/ SHARED CONTROL BUS iNTEGRATED Plastic Encapsulated Microcircuit DDR2 Data rate = 667, 533, 400 Available in Industrial, Enhanced and Extended Temp Package: • Proprietary Enchanced Die Stacked iPEM • 208 Plastic Ball Grid Array (PBGA), 16 x 23mm • 1.00mm ball pitch Differential data strobe (DQS, DQS#) per by |
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Austin Semiconductor |
64Mx72 DDR2 SDRAM w/ SHARED CONTROL BUS iNTEGRATED Plastic Encapsulated Microcircuit DDR2 Data rate = 667, 533, 400 Available in Industrial, Enhanced and Military Temp Package: • Proprietary Enchanced Die Stacked iPEM • 208 Plastic Ball Grid Array (PBGA), 16 x 23mm • 1.00mm ball pitch Differential data strobe (DQS, DQS#) per by |
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Austin Semiconductor |
32Mx72 DDR SDRAM iNTEGRATED Plastic Encapsulated Microcircuit DDR SDRAM Data Rate = 200, 250, 266, 333Mbps Package: BENEFITS 40 - 70% SPACE SAVINGS Reduced part count Reduced I/O count • 208 Plastic Ball Grid Array (PBGA), 16 x 23mm-1.0mm pitch 2.5V ±0.2V core pow |
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Austin Semiconductor |
128 Mb: 8 Meg x 16 SDRAM • Full Military temp (-55°C to 125°C) processing available • Configuration: 8 Meg x 16 (2 Meg x 16 x 4 banks) • Fully synchronous; all signals registered on positive edge of system clock • Internal pipelined operation; column address can be changed e |
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Austin Semiconductor |
64K x 4 DRAM |
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Austin Semiconductor |
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Austin Semiconductor |
16M FPM DRAM • Fast Page Mode Operation • CAS\-before-RAS\ Refresh Capability • RAS\-only and Hidden Refresh Capability • Self-refresh Capability • Fast Parallel Test Mode Capability • TTL Compatible Inputs and Outputs • Early Write or Output Enable Controlled Wr |
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Austin Semiconductor |
16Mx72 DDR SDRAM iNTEGRATED Plastic Encapsulated Microcircuit DDR SDRAM Data Rate = 200, 250, 266, 333Mbps Package: BENEFITS 40% SPACE SAVINGS Reduced part count Reduced I/O count • 219 Plastic Ball Grid Array (PBGA), 32 x 25mm 2.5V ±0.2V core power supply 2.5V I/ |
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Desde 2024. D4U Semiconductor.
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