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AS4DDR16M72PBG |
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| Part Number | AS4DDR16M72PBG |
| Manufacturer | Austin Semiconductor |
| Description | BGA Locations SYMBOL F4, F16, G5, G15, K1, K12, CKx, CKx L2, L13, N6, M8 DESCRIPTION Clock: CKx and CKx are differential clock inputs. All address and control input signals are sampled on the crossing... |
| Features |
DDR SDRAM Data Rate = 200, 250, 266, 333Mbps Package:
BENEFITS
40% SPACE SAVINGS Reduced part count Reduced I/O count
• 219 Plastic Ball Grid Array (PBGA), 32 x 25mm 2.5V ±0.2V core power supply 2.5V I/O (SSTL_2 compatible) Differential clock inputs (CLK and CLK#) Commands entered on each positive CLK edge Internal pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle Programmable Burst length: 2,4 or 8 Bidirectional data strobe (DQS) transmitted/received with data, i.e., source-synchronous data capture (one per byte) D... |
| Document |
 AS4DDR16M72PBG Data Sheet
PDF 403.15KB |
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Desde 2024. D4U Semiconductor.
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