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Toshiba Semiconductor |
MOSFETs (1) (2) (3) (4) AEC-Q101 qualified Low drain-source on-resistance: RDS(ON) = 33.8 mΩ (typ.) (VGS = -10 V) Low leakage current: IDSS = -10 µA (max) (VDS = -40 V) Enhancement mode: Vth = -2.0 to -3.0 V (VDS = -10 V, ID = -1 mA) 3. Packaging and Intern |
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Toshiba Semiconductor |
MOSFETs (1) (2) (3) Low drain-source on-resistance: RDS(ON) = 5.6 mΩ (typ.) (VGS = -10 V) Low leakage current: IDSS = -10 µA (max) (VDS = -60 V) Enhancement mode: Vth = -2.0 to -3.0 V (VDS = -10 V, ID = -1 mA) 3. Packaging and Internal Circuit 1: Gate 2: D |
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Toshiba Semiconductor |
MOSFETs (1) (2) (3) Low drain-source on-resistance: RDS(ON) = 2.2 mΩ (typ.) (VGS = -10 V) Low leakage current: IDSS = -10 µA (max) (VDS = -40 V) Enhancement mode: Vth = -2.0 to -3.0 V (VDS = -10 V, ID = -1 mA) 3. Packaging and Internal Circuit 1: Gate 2: D |
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Toshiba Semiconductor |
MOSFETs (1) (2) (3) Low drain-source on-resistance: RDS(ON) = 2.8 mΩ (typ.) (VGS = -10 V) Low leakage current: IDSS = -10 µA (max) (VDS = -40 V) Enhancement mode: Vth = -2.0 to -3.0 V (VDS = -10 V, ID = -1 mA) 3. Packaging and Internal Circuit 1: Gate 2: D |
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Toshiba Semiconductor |
P-Channel MOSFET ngle pulse avalanche energy (Note 2) Avalanche current Repetitive avalanche energy (Note 3) Channel temperature (Note 4) Storage temperature range (Note 4) JEDEC JEITA TOSHIBA ⎯ ⎯ 2-10W1A Weight: 1.07 g (typ.) 2 Thermal Characteristics Characteri |
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Toshiba |
MOSFETs Silicon P-Channel MOS (1) (2) (3) Low drain-source on-resistance: RDS(ON) = 100 mΩ (typ.) (VGS = -10 V) Low leakage current: IDSS = -10 µA (max) (VDS = -100 V) Enhancement mode: Vth = -2.0 to -4.0 V (VDS = -10 V, ID = -1 mA) 3. Packaging and Internal Circuit 1: Gate 2: |
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Toshiba |
P-Channel MOSFET (1) AEC-Q101 qualified (2) Low drain-source on-resistance: RDS(ON) = 38.5 mΩ (typ.) (VGS = -10 V) (3) Low leakage current: IDSS = -10 µA (max) (VDS = -60 V) (4) Enhancement mode: Vth = -2.0 to -3.0 V (VDS = -10 V, ID = -1 mA) 3. Packaging and Interna |
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Toshiba Semiconductor |
MOSFETs (1) (2) (3) Low drain-source on-resistance: RDS(ON) = 4.3 mΩ (typ.) (VGS = -10 V) Low leakage current: IDSS = -10 µA (max) (VDS = -60 V) Enhancement mode: Vth = -2.0 to -3.0 V (VDS = -10 V, ID = -1 mA) 3. Packaging and Internal Circuit 1: Gate 2: D |
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Desde 2024. D4U Semiconductor.
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