| No. | parte # | Fabricante | Descripción | Hoja de Datos |
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Nanya Techology |
(NT5DSxxMxBx) 256Mb DDR SDRAM CAS Latency and Frequency CAS Latency 3 2.5 Maximum Operating Frequency (MHz) DDR400B (-5T) 200 166 • • • • • • • • • • • • • • Double data rate architecture: two data transfers per clock cycle • Bidirectional data strobe (DQS) is transmitted and r |
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Nanya Techology |
256Mb SDRAM CAS Latency and Frequency CAS Latency 2 2.5 3 Maximum Operating Frequency (MHz) DDR400 DDR333 (5T) (6K/6KL) 133 166 166 200 - • • • • • • • • • • • • • • • DDR 256M bit, die C, based on 110nm design rules • Double data rate architecture: two data t |
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Nanya Techology |
(NT5DSxxMxBx) 512Mb DDR SDRAM CAS Latency and Frequency CAS Latency 2 2.5 3 Maximum Operating Frequency (MHz) DDR400 DDR333 DDR266B (5T) (6K) (75B) 133 100 166 166 133 200 - • • • • • • • • • • • • • • DDR 512M bit, die B, based on 110nm design rules • Double data rate architec |
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Nanya Techology |
(NT5DS16M8AT / NT5DS32M4AT) 128Mb DDR SDRAM CAS Latency and Frequency Maximum Operating Frequency (MHz)* DDR266A DDR266B DDR200 (-7K) (-75B) (-8B) 2 133 100 100 2.5 143 133 125 * Values are nominal (exact tCK should be used). CAS Latency • Double data rate architecture: two data transfers per |
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Nanya Techology |
(NT5DSxxMxBx) 256Mb DDR SDRAM CAS Latency and Frequency CAS Latency 3 2.5 Maximum Operating Frequency (MHz) DDR400B (-5T) 200 166 • • • • • • • • • • • • • • Double data rate architecture: two data transfers per clock cycle • Bidirectional data strobe (DQS) is transmitted and r |
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Nanya Techology |
(NT5DSxxMxBx) 512Mb DDR SDRAM CAS Latency and Frequency CAS Latency 2 2.5 3 Maximum Operating Frequency (MHz) DDR400 DDR333 DDR266B (5T) (6K) (75B) 133 100 166 166 133 200 - • • • • • • • • • • • • • • DDR 512M bit, die B, based on 110nm design rules • Double data rate architec |
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Nanya Techology |
(NT5DSxxMxBx) 512Mb DDR SDRAM CAS Latency and Frequency CAS Latency 2 2.5 3 Maximum Operating Frequency (MHz) DDR400 DDR333 DDR266B (5T) (6K) (75B) 133 100 166 166 133 200 - • • • • • • • • • • • • • • DDR 512M bit, die B, based on 110nm design rules • Double data rate architec |
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Nanya Techology |
512Mb DDR SDRAM • DDR 512M bit, Die C, based on 90nm design rules • Double data rate architecture: two data transfers per clock cycle • Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver • DQS is edge- |
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Nanya Techology |
512Mb DDR SDRAM • DDR 512M bit, Die C, based on 90nm design rules • Double data rate architecture: two data transfers per clock cycle • Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver • DQS is edge- |
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Nanya Techology |
(NT5DSxxMxBx) 256Mb DDR SDRAM CAS Latency and Frequency CAS Latency 3 2.5 Maximum Operating Frequency (MHz) DDR400A DDR400B (-5) (-5T) 200 200 200 166 • • • • • • • • • • • • • • Double data rate architecture: two data transfers per clock cycle • Bidirectional data strobe (DQS) |
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Nanya Techology |
(NT5DSxxMxBx) 256Mb DDR SDRAM CAS Latency and Frequency CAS Latency 3 2.5 Maximum Operating Frequency (MHz) DDR400B (-5T) 200 166 • • • • • • • • • • • • • • Double data rate architecture: two data transfers per clock cycle • Bidirectional data strobe (DQS) is transmitted and r |
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Nanya Techology |
(NT5DSxxMxBx) 256Mb DDR SDRAM CAS Latency and Frequency CAS Latency 3 2.5 Maximum Operating Frequency (MHz) DDR400B (-5T) 200 166 • • • • • • • • • • • • • • Double data rate architecture: two data transfers per clock cycle • Bidirectional data strobe (DQS) is transmitted and r |
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Nanya Techology |
256Mb SDRAM CAS Latency and Frequency CAS Latency 2 2.5 3 Maximum Operating Frequency (MHz) DDR400 DDR333 (5T) (6K/6KL) 133 166 166 200 - • • • • • • • • • • • • • • • DDR 256M bit, die C, based on 110nm design rules • Double data rate architecture: two data t |
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Nanya Techology |
256Mb SDRAM CAS Latency and Frequency CAS Latency 2 2.5 3 Maximum Operating Frequency (MHz) DDR400 DDR333 (5T) (6K/6KL) 133 166 166 200 - • • • • • • • • • • • • • • • DDR 256M bit, die C, based on 110nm design rules • Double data rate architecture: two data t |
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Nanya Techology |
(NT5DSxxMxAF) 512Mb DDR SDRAM CAS Latency and Frequency CAS Latency 2 2.5 Maximum Operating Frequency (MHz) DDR333 DDR266B 6K 75B 133 100 166 133 • • • • • • • • • • • • • • • Double data rate architecture: two data transfers per clock cycle • Bidirectional data strobe (DQS) is |
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Nanya Techology |
(NT5DSxxMxBx) 512Mb DDR SDRAM CAS Latency and Frequency CAS Latency 2 2.5 3 Maximum Operating Frequency (MHz) DDR400 DDR333 DDR266B (5T) (6K) (75B) 133 100 166 166 133 200 - • • • • • • • • • • • • • • DDR 512M bit, die B, based on 110nm design rules • Double data rate architec |
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Nanya Techology |
(NT5DSxxMxBx) 512Mb DDR SDRAM CAS Latency and Frequency CAS Latency 2 2.5 3 Maximum Operating Frequency (MHz) DDR400 DDR333 DDR266B (5T) (6K) (75B) 133 100 166 166 133 200 - • • • • • • • • • • • • • • DDR 512M bit, die B, based on 110nm design rules • Double data rate architec |
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Nanya Techology |
512Mb DDR SDRAM • DDR 512M bit, Die C, based on 90nm design rules • Double data rate architecture: two data transfers per clock cycle • Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver • DQS is edge- |
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Nanya Techology |
512Mb DDR SDRAM • DDR 512M bit, Die C, based on 90nm design rules • Double data rate architecture: two data transfers per clock cycle • Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver • DQS is edge- |
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Nanya Techology |
512Mb DDR SDRAM • DDR 512M bit, Die C, based on 90nm design rules • Double data rate architecture: two data transfers per clock cycle • Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver • DQS is edge- |
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Desde 2024. D4U Semiconductor.
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