Qimonda HYB Hoja de datos

No.	parte #	Fabricante	Descripción
1	HYB25D512400DT	Qimonda	512M DDR SDRAM Double data rate architecture: two data transfers per clock cycle Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver DQS is edge-aligned with data for reads and is center-aligned with
2	HYB25D512800CT	Qimonda	(HYB25D512xx0Cx) DDR SDRAM • • • • • • • • • • • • Burst Lengths: 2, 4, or 8 CAS Latency: 2, 2.5, 3 Auto Precharge option for each burst access Auto Refresh and Self Refresh Modes RAS-lockout supported tRAP=tRCD 7.8 µs Maximum Average Periodic Refresh Interval 2.5 V (SSTL_2 co
3	HYB18T1G800BF	Qimonda	1-Gbit Double-Data-Rate-Two SDRAM The 1-Gbit Double-data-Rate SDRAM offers the following key features: • Off-Chip-Driver impedance adjustment (OCD) and On • 1.8 V ± 0.1 V Power Supply 1.8 V ± 0.1 V (SSTL_18) compatible I/O Die-Termination (ODT) for better signal quality • DRAM organi
4	HYB18T1G800BC	Qimonda	1-Gbit Double-Data-Rate-Two SDRAM The 1-Gbit Double-data-Rate SDRAM offers the following key features: • Off-Chip-Driver impedance adjustment (OCD) and On • 1.8 V ± 0.1 V Power Supply 1.8 V ± 0.1 V (SSTL_18) compatible I/O Die-Termination (ODT) for better signal quality • DRAM organi
5	HYB18T1G160BC	Qimonda	1-Gbit Double-Data-Rate-Two SDRAM The 1-Gbit Double-data-Rate SDRAM offers the following key features: • Off-Chip-Driver impedance adjustment (OCD) and On • 1.8 V ± 0.1 V Power Supply 1.8 V ± 0.1 V (SSTL_18) compatible I/O Die-Termination (ODT) for better signal quality • DRAM organi
6	HYB18T512160B	Qimonda	512-Mbit Double-Data-Rate-Two SDRAM The 512-Mbit Double-Data-Rate-Two SDRAM offers the following key features: • Off-Chip-Driver impedance adjustment (OCD) and On • 1.8 V ± 0.1 V Power Supply 1.8 V ± 0.1 V (SSTL_18) compatible I/O Die-Termination (ODT) for better signal quality • DRAM
7	HYB25D512800BF	Qimonda	(HYB25D512xx0Bx) 512-Mbit Double-Data-Rate SDRAM
8	HYB25D512800CC	Qimonda	(HYB25D512xx0Cx) DDR SDRAM • • • • • • • • • • • • Burst Lengths: 2, 4, or 8 CAS Latency: 2, 2.5, 3 Auto Precharge option for each burst access Auto Refresh and Self Refresh Modes RAS-lockout supported tRAP=tRCD 7.8 µs Maximum Average Periodic Refresh Interval 2.5 V (SSTL_2 co
9	HYB25D512800CE	Qimonda	(HYB25D512xx0Cx) DDR SDRAM • • • • • • • • • • • • Burst Lengths: 2, 4, or 8 CAS Latency: 2, 2.5, 3 Auto Precharge option for each burst access Auto Refresh and Self Refresh Modes RAS-lockout supported tRAP=tRCD 7.8 µs Maximum Average Periodic Refresh Interval 2.5 V (SSTL_2 co
10	HYB25D512400DF	Qimonda	512M DDR SDRAM Double data rate architecture: two data transfers per clock cycle Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver DQS is edge-aligned with data for reads and is center-aligned with
11	HYB18T1G400BF	Qimonda	1-Gbit Double-Data-Rate-Two SDRAM The 1-Gbit Double-data-Rate SDRAM offers the following key features: • Off-Chip-Driver impedance adjustment (OCD) and On • 1.8 V ± 0.1 V Power Supply 1.8 V ± 0.1 V (SSTL_18) compatible I/O Die-Termination (ODT) for better signal quality • DRAM organi
12	HYB18T1G400BC	Qimonda	1-Gbit Double-Data-Rate-Two SDRAM The 1-Gbit Double-data-Rate SDRAM offers the following key features: • Off-Chip-Driver impedance adjustment (OCD) and On • 1.8 V ± 0.1 V Power Supply 1.8 V ± 0.1 V (SSTL_18) compatible I/O Die-Termination (ODT) for better signal quality • DRAM organi
13	HYB25DC512800BF	Qimonda	512-Mbit Double-Data-Rate SDRAM This chapter lists all main features of the product family HYB25DC512[80/16]0B[E/F] and the ordering information. Double data rate architecture: two data transfers per clock cycle Bidirectional data strobe (DQS) is transmitted and received with dat
14	HYB18T512400B	Qimonda	512-Mbit Double-Data-Rate-Two SDRAM The 512-Mbit Double-Data-Rate-Two SDRAM offers the following key features: • Off-Chip-Driver impedance adjustment (OCD) and On • 1.8 V ± 0.1 V Power Supply 1.8 V ± 0.1 V (SSTL_18) compatible I/O Die-Termination (ODT) for better signal quality • DRAM
15	HYB18T512400BC	Qimonda	512-Mbit Double-Data-Rate-Two SDRAM The 512-Mbit Double-Data-Rate-Two SDRAM offers the following key features: • Off-Chip-Driver impedance adjustment (OCD) and On • 1.8 V ± 0.1 V Power Supply 1.8 V ± 0.1 V (SSTL_18) compatible I/O Die-Termination (ODT) for better signal quality • DRAM
16	HYB39S128160FE	Qimonda	128-MBit Synchronous DRAM • • • • • • • • • Data Mask for Read / Write control (x4, x8) Data Mask for Byte Control (x16) Auto Refresh (CBR) and Self Refresh Power Down and Clock Suspend Mode 4096 refresh cycles / 64 ms (15.6 μs) Random Column Address every CLK (1-N Rule) Sing
17	HYB39S128160FEL	Qimonda	128-MBit Synchronous DRAM • • • • • • • • • Data Mask for Read / Write control (x4, x8) Data Mask for Byte Control (x16) Auto Refresh (CBR) and Self Refresh Power Down and Clock Suspend Mode 4096 refresh cycles / 64 ms (15.6 μs) Random Column Address every CLK (1-N Rule) Sing
18	HYB39S128800FEL	Qimonda	128-MBit Synchronous DRAM • • • • • • • • • Data Mask for Read / Write control (x4, x8) Data Mask for Byte Control (x16) Auto Refresh (CBR) and Self Refresh Power Down and Clock Suspend Mode 4096 refresh cycles / 64 ms (15.6 μs) Random Column Address every CLK (1-N Rule) Sing
19	HYB39S128800FTL	Qimonda	128-MBit Synchronous DRAM • • • • • • • • • Data Mask for Read / Write control (x4, x8) Data Mask for Byte Control (x16) Auto Refresh (CBR) and Self Refresh Power Down and Clock Suspend Mode 4096 refresh cycles / 64 ms (15.6 μs) Random Column Address every CLK (1-N Rule) Sing
20	HYB39S128400FT	Qimonda	128-MBit Synchronous DRAM • • • • • • • • • Data Mask for Read / Write control (x4, x8) Data Mask for Byte Control (x16) Auto Refresh (CBR) and Self Refresh Power Down and Clock Suspend Mode 4096 refresh cycles / 64 ms (15.6 μs) Random Column Address every CLK (1-N Rule) Sing