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HYB18T1G160BC |
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| Part Number | HYB18T1G160BC |
| Manufacturer | Qimonda |
| Description | Inputs are latched at the cross point of differential clocks (CK rising and CK falling). All I/Os are synchronized with a single ended DQS or differential DQS-DQS pair in a source synchronous fashion.... |
| Features |
The 1-Gbit Double-data-Rate SDRAM offers the following key features: • Off-Chip-Driver impedance adjustment (OCD) and On • 1.8 V ± 0.1 V Power Supply 1.8 V ± 0.1 V (SSTL_18) compatible I/O Die-Termination (ODT) for better signal quality • DRAM organizations with 4, 8 and 16 data in/outputs • Auto-Precharge operation for read and write bursts • Double Data Rate architecture: two data transfers per • Auto-Refresh, Self-Refresh and power saving Powerclock cycle four internal banks for concurrent operation Down modes • Programmable CAS Latency: 3, 4, 5 and 6 • Average Refresh Period 7.8 µs at a TC... |
| Document |
 HYB18T1G160BC Data Sheet
PDF 3.86MB |
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Desde 2024. D4U Semiconductor.
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