| No. | parte # | Fabricante | Descripción | Hoja de Datos |
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Motorola |
PRESETTABLE BCD/DECADE UP/DOWN COUNTER simplifies the design of multi-stage counters, as indicated in Figures a and b. In Figure a, each RC output is used as the clock input for the next higher stage. This configuration is particularly advantageous when the clock source has a limited driv |
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Motorola Inc |
QUAD 2-INPUT AND GATE |
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Motorola Inc |
TRIPLE 3-INPUT NAND GATE – 0.4 –100 1.2 3.3 0.35 0.5 20 IIH IIL IOS ICC V µA mA mA mA 2.7 3.5 0.25 0.4 V V 2.5 – 0.65 3.5 0.8 – 1.5 V V Min 2.0 0.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC |
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Motorola Inc |
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP Set) Hold L H L H H H H CD H L L H H H H J X X X h l h l K X X X h h l l Q H L H q L H q Q L H H q H L q 3 OUTPUTS SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC LOGIC SYMBOL 4 10 * Both outputs will be HIGH while both SD and CD are LOW, |
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Motorola Inc |
TRIPLE 3-INPUT NAND GATE 5 0.5 20 IIH IIL ICC V µA mA mA 54, 74 54, 74 0.25 – 0.65 0.8 – 1.5 100 0.4 V µA V Min 2.0 0.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN, IIN = – 18 mA VCC = MI |
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Motorola Inc |
8-INPUT MULTIPLEXER r Output (Note b) Complementary Multiplexer Output (Note b) LOADING (Note a) HIGH 0.5 U.L. 0.5 U.L. 0.5 U.L. 10 U.L. 10 U.L. LOW 0.25 U.L. 0.25 U.L. 0.25 U.L. 5 (2.5) U.L. 5 (2.5) U.L. LOGIC SYMBOL 7 4 3 2 1 15 14 13 12 E I0 I1 I2 I3 I4 I5 I6 I7 S0 |
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Motorola Inc |
DUAL 4-INPUT MULTIPLEXER a 7 Za 8 GND 16 1 N SUFFIX PLASTIC CASE 648-08 PIN NAMES S0 E I0, I1 Z Common Select Input Enable (Active LOW) Input Multiplexer Inputs Multiplexer Output (Note b) LOADING (Note a) HIGH 0.5 U.L. 0.5 U.L. 0.5 U.L. 10 U.L. LOW 0.25 U.L. 0.25 U.L. |
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Motorola |
10-LINE-TO-4-LINE AND 8-LINE-TO-3-LINE PRIORITY ENCODERS |
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Motorola Inc |
UNIVERSAL 4-BIT SHIFT REGISTER 25 U.L. 5 (2.5) U.L. 5 (2.5) U.L. 1 D SUFFIX SOIC CASE 751B-03 PE P0 – P3 J K CP MR Q0 – Q3 Q3 Parallel Enable (Active LOW) Input Parallel Data Inputs First Stage J (Active HIGH) Input First Stage K (Active LOW) Input Clock (Active HIGH Going Edg |
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Motorola Inc |
8-BIT SHIFT/STORAGE REGISTER 8 Q 7 17 I/O 7 16 I/O 5 15 I/O 3 14 I/O 1 13 CP 12 DS 0 11 20 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. 1 DW SUFFIX SOIC CASE 751D-03 ORDERING INFORMATION SN54LSXXXJ Ceramic SN74LSXXXN Plastic |
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Motorola Inc |
4-BIT SHIFT REGISTER 14 1 N SUFFIX PLASTIC CASE 646-06 VCC = PIN 14 GND = PIN 7 1 DS 2 P0 3 P1 4 P2 5 P3 6 S 7 GND 14 1 D SUFFIX SOIC CASE 751A-02 PIN NAMES LOADING (Note a) HIGH LOW 0.25 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 5 (2.5) U.L. ORDERING INFORMA |
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Motorola |
BCD DECADE COUNTERS / 4-BIT BINARY COUNTERS The counters consist of four edge-triggered D flip-flops with the appropriate data routing networks feeding the D inputs. All changes of the Q outputs (except due to the asynchronous Master Reset in the LS160A and LS161A) occur as a result of, and s |
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Motorola Inc |
QUAD 2-INPUT NAND GATE HIGH Total, Output LOW Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. Min 2.0 Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC |
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Motorola Inc |
TRIPLE 3-INPUT AND GATE 0.4 –100 3.6 6.6 0.35 0.5 20 IIH IIL IOS ICC V µA mA mA mA 2.7 3.5 0.25 0.4 V V 2.5 – 0.65 3.5 0.8 – 1.5 V V Min 2.0 0.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = M |
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Motorola Inc |
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP individual J, K, clock, and asynchronous set and clear inputs to each flip-flop. When the clock goes HIGH, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may be allowed to change when the clock pulse is HIGH a |
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Motorola Inc |
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP 4LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC LOGIC SYMBOL 4 10 H, h = HIGH Voltage Level L, I = LOW Voltage Level X = Don’t Care l, h (q) = Lower case letters indicate the state of the referenced input (or output) l, h (q) = one set-up time |
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Motorola Inc |
RETRIGGERABLE MONOSTABLE MULTIVIBRATORS pulse width control by three methods. The basic pulse width is programmed by selection of external resistance and capacitance values. The LS122 has an internal timing resistor that allows the circuits to be used with only an external capacitor. Once |
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Motorola Inc |
QUAD 2-INPUT MULTIPLEXER I0b 6 I1b 7 Zb 8 GND 16 1 N SUFFIX PLASTIC CASE 648-08 PIN NAMES S E I0a – I0d I1a – I1d Za – Zd Common Select Input Enable (Active LOW) Input Data Inputs from Source 0 Data Inputs from Source 1 Inverted Outputs (Note b) LOADING (Note a) HIGH |
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Motorola Inc |
BCD DECADE COUNTERS/ 4-BIT BINARY COUNTERS The counters consist of four edge-triggered D flip-flops with the appropriate data routing networks feeding the D inputs. All changes of the Q outputs (except due to the asynchronous Master Reset in the LS160A and LS161A) occur as a result of, and s |
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Motorola Inc |
DUAL 4-INPUT NAND GATE IIH IIL ICC V µA mA mA 54, 74 54, 74 0.25 – 0.65 0.8 – 1.5 100 0.4 V µA V Min 2.0 0.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN, IIN = – 18 mA VCC = MIN, VOH = |
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Desde 2024. D4U Semiconductor.
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