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SN54LS112A |
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| Part Number | SN54LS112A |
| Manufacturer | Motorola Inc |
| Description | SN54/74LS112A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS112A dual JK flip-flop features individual J, K, clock, and asynchronous set and clear inputs to each flip-flop. When the clock g... |
| Features |
individual J, K, clock, and asynchronous set and clear inputs to each flip-flop. When the clock goes HIGH, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may be allowed to change when the clock pulse is HIGH and the bistable will perform according to the truth table as long as minimum set-up and hold time are observed. Input data is transferred to the outputs on the negative-going edge of the clock pulse.
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
LOW POWER SCHOTTKY
LOGIC DIAGRAM (Each Flip-Flop)
J SUFFIX CERAMIC CASE 620-09
16 1
Q 5(9) 6(7)
Q
CLEA... |
| Document |
 SN54LS112A Data Sheet
PDF 147.34KB |
Similar Datasheet
| No. | Parte # | Fabricante | Descripción | Hoja de Datos |
|---|---|---|---|---|
| 1 | SN54LS112A |
Texas Instruments |
Dual J-K Negative-Edge-Triggered Flip-Flops |
|
| 2 | SN54LS11 |
Motorola Inc |
TRIPLE 3-INPUT AND GATE |
|
| 3 | SN54LS11 |
Texas Instruments |
TRIPLE 3-INPUT POSITIVE-AND GATES |
|
| 4 | SN54LS113A |
Motorola Inc |
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP |
|
| 5 | SN54LS114A |
Motorola Inc |
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP |
|
| 6 | SN54LS10 |
Motorola Inc |
TRIPLE 3-INPUT NAND GATE |
|
Desde 2024. D4U Semiconductor.
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