Hitachi Semiconductor 74L Hoja de datos

No.	parte #	Fabricante	Descripción
1	74LS02	Hitachi Semiconductor	Quadruple 2-input Positive NOR Gates rty rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document
2	HD74LVC374A	Hitachi Semiconductor	Octal D-type Flip Flops with 3-state Outputs • • • • • • VCC = 2.0 V to 5.5 V All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V) All outputs VOUT (Max.) = 5.5 V (@VCC = 0 V or output off state) Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25 °C) Typical VOH undershoot > 2.0 V (@VCC =
3	74LS112	Hitachi Semiconductor	Dual J-K Negative-edge-triggered Flip-Flops s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual prope
4	74LVC245	Hitachi Semiconductor	Octal Bidirectional Transceivers • • • • • • VCC = 2.0 V to 5.5 V All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V) All input outputs VI/O (Max.) = 5.5 V (@VCC = 0 V or output off state) Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C) Typical VOH undershoot > 2.0 V (@V
5	HD74LS160A	Hitachi Semiconductor	Synchronous Decade Counters s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual prope
6	HD74LS114	Hitachi Semiconductor	Dual J-K Negative-edge-triggered Flip-Flops rty rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document
7	HD74LVC16245A	Hitachi Semiconductor	16-bit Bus Transceivers with 3-state Outputs • • • • • • VCC = 2.0 V to 5.5 V All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V) All outputs VOUT (Max.) = 5.5 V (@VCC = 0 V or output off state) Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C) Typical VOH undershoot > 2.0 V (@VCC = 3
8	74LS191	Hitachi Semiconductor	Synchronous Up/Down 4-bit Binary Counters s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual prope
9	74LS121	Hitachi Semiconductor	Dual Retriggerable Monostable Multivibrators om Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibili
10	HD74LS08	Hitachi Semiconductor	Quadruple 2-input Positive AND Gates • Ordering Information Part Name Package Type Package Code (Previous Code) Package Abbreviation HD74LS08P DILP-14 pin PRDP0014AB-B (DP-14AV) P HD74LS08FPEL SOP-14 pin (JEITA) PRSP0014DF-B (FP-14DAV) FP HD74LS08RPEL SOP-14 pin (JEDEC) PR
11	HD74LV393A	Hitachi Semiconductor	Dual 4-bit Binary Counters • • • • • • VCC = 2.0 V to 5.5 V operation All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V) All outputs VO (Max.) = 5.5 V (@VCC = 0 V) Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C) Typical VOH undershoot > 2.3 V (@VCC = 3.3 V, Ta = 2
12	74LS01	Hitachi Semiconductor	Quadruple 2-input Positive NAND Gates rty rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document
13	74LS12	Hitachi Semiconductor	Dual Retriggerable Monostable Multivibrators s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual prope
14	74LS48	Hitachi Semiconductor	BCD-to-Seven-Segment Decoder Driver rty rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document
15	HD74LS00	Hitachi Semiconductor	Quadruple 2-Input NAND Gates Ordering Information Part Name Package Type Package Code Package (Previous Code) Abbreviation HD74LS00P DILP-14 pin PRDP0014AB-B (DP-14AV) P HD74LS00FPEL SOP-14 pin (JEITA) PRSP0014DF-B (FP-14DAV) FP HD74LS00RPEL SOP-14 pin (JEDEC) PRSP0
16	74LS139	Hitachi Semiconductor	Dual 2-line-to-4-line Decoders/Demultiplexers s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual prope
17	74LS192	Hitachi Semiconductor	Synchronous Up/Down Decade Counters s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual prope
18	74LS373	Hitachi Semiconductor	Octal D-type Transparent Latches any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property
19	74LS76	Hitachi Semiconductor	Dual J-K Flip-Flop s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual prope
20	74LS86	Hitachi Semiconductor	Quadruple 2-input Exclusive-OR Gates rty rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document