Samsung Semiconductor K4H Hoja de datos

No.	parte #	Fabricante	Descripción
1	K4H560438H	Samsung semiconductor	(K4H560438H - K4H561638H) 256Mb H-die DDR SDRAM Specification .............................................................................................................................. 4 2.0 Ordering Information ................................................................................................
2	K4H511638D-LA2	Samsung semiconductor	512Mb D-die DDR SDRAM Specification 66 TSOP-II ...............................................................................................................................4 2.0 Ordering Information ................................................................................................
3	K4H561638F-UCC4	Samsung semiconductor	256Mb F-die DDR400 SDRAM • 200MHz Clock, 400Mbps data rate. • VDD= +2.6V + 0.10V, VDDQ= +2.6V + 0.10V • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL alig
4	K4H561638H	Samsung semiconductor	(K4H560438H - K4H561638H) 256Mb H-die DDR SDRAM Specification .............................................................................................................................. 4 2.0 Ordering Information ................................................................................................
5	K4H1G0838A	Samsung semiconductor	(K4H1G0438A / K4H1G0838A) 1Gb A-die SDRAM Specification .............................................................................................................................. 4 2.0 Ordering Information ................................................................................................
6	K4H510438D	Samsung semiconductor	(K4H51xx38D) 512Mb D-die DDR SDRAM Specification ...............................................................................................................................4 2.0 Ordering Information ................................................................................................
7	K4H510838D	Samsung semiconductor	(K4H51xx38D) 512Mb D-die DDR SDRAM Specification ...............................................................................................................................4 2.0 Ordering Information ................................................................................................
8	K4H511638D	Samsung semiconductor	(K4H51xx38D) 512Mb D-die DDR SDRAM Specification ...............................................................................................................................4 2.0 Ordering Information ................................................................................................
9	K4H510838D-LCC	Samsung semiconductor	512Mb D-die DDR SDRAM Specification 66 TSOP-II ...............................................................................................................................4 2.0 Ordering Information ................................................................................................
10	K4H511638D-LB3	Samsung semiconductor	512Mb D-die DDR SDRAM Specification 66 TSOP-II ...............................................................................................................................4 2.0 Ordering Information ................................................................................................
11	K4H511638D-LCC	Samsung semiconductor	512Mb D-die DDR SDRAM Specification 66 TSOP-II ...............................................................................................................................4 2.0 Ordering Information ................................................................................................
12	K4H561638F	Samsung semiconductor	256Mb F-die DDR SDRAM Specification • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe L(U)DQS • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key p
13	K4H560838F-TCCC	Samsung semiconductor	256Mb F-die DDR400 SDRAM Specification • 200MHz Clock, 400Mbps data rate. • VDD= +2.6V + 0.10V, VDDQ= +2.6V + 0.10V • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL alig
14	K4H560838F-TCC4	Samsung semiconductor	256Mb F-die DDR400 SDRAM Specification • 200MHz Clock, 400Mbps data rate. • VDD= +2.6V + 0.10V, VDDQ= +2.6V + 0.10V • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL alig
15	K4H561638F-TCCC	Samsung semiconductor	256Mb F-die DDR400 SDRAM Specification • 200MHz Clock, 400Mbps data rate. • VDD= +2.6V + 0.10V, VDDQ= +2.6V + 0.10V • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL alig
16	K4H561638F-TCC4	Samsung semiconductor	256Mb F-die DDR400 SDRAM Specification • 200MHz Clock, 400Mbps data rate. • VDD= +2.6V + 0.10V, VDDQ= +2.6V + 0.10V • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL alig
17	K4H560838F-UCCC	Samsung semiconductor	256Mb F-die DDR400 SDRAM • 200MHz Clock, 400Mbps data rate. • VDD= +2.6V + 0.10V, VDDQ= +2.6V + 0.10V • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL alig
18	K4H560838F-UCC4	Samsung semiconductor	256Mb F-die DDR400 SDRAM • 200MHz Clock, 400Mbps data rate. • VDD= +2.6V + 0.10V, VDDQ= +2.6V + 0.10V • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL alig
19	K4H561638F-UCCC	Samsung semiconductor	256Mb F-die DDR400 SDRAM • 200MHz Clock, 400Mbps data rate. • VDD= +2.6V + 0.10V, VDDQ= +2.6V + 0.10V • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL alig
20	K4H560838F-TC	Samsung Semiconductor	DDR SDRAM 256Mb F-die • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe L(U)DQS • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key p