Qimonda AG HYB Hoja de datos

No.	parte #	Fabricante	Descripción
1	HYB18L512160BF-7.5	Qimonda AG	DRAMs for Mobile Applications 512-Mbit Mobile-RAM 4 banks × 8 Mbit × 16 organization Fully synchronous to positive clock edge Four internal banks for concurrent operation Programmable CAS latency: 2, 3 Programmable burst length: 1, 2, 4, 8 or full page Programmable wrap sequence: sequential or inte
2	HYB18H512321BF-10	Qimonda AG	512-Mbit GDDR3 Graphics RAM • Data mask for write commands • Single ended READ strobe (RDQS) per byte. RDQS edgealigned with READ data • Single ended WRITE strobe (WDQS) per byte. WDQS center-aligned with WRITE data • DLL aligns RDQS and DQ transitions with Clock • Programmable
3	HYB18L512320BF-7.5	Qimonda AG	DRAMs for Mobile Applications 512-Mbit SDR Mobile-RAM 4 banks × 4 Mbit × 32 organization (dual-die) Fully synchronous to positive clock edge Four internal banks for concurrent operation Programmable CAS latency: 2, 3 Programmable burst length: 1, 2, 4, 8 or full page Programmable wrap sequence: sequent
4	HYB18T256161BF-20	Qimonda AG	256-Mbit x16 DDR2 SDRAM The 256-Mbit Double-Data-Rate-Two SDRAM offers the following key features: • Data masks (DM) for write data • 1.8 V ± 0.1V VDD for [ –20/ –25/ –28] • 1.8 V ± 0.1V VDDQ for [ –20/ –25/ –28] • Posted CAS by programmable additive latency for better • DRAM or
5	HYB18T256161BF-25	Qimonda AG	256-Mbit x16 DDR2 SDRAM The 256-Mbit Double-Data-Rate-Two SDRAM offers the following key features: • Data masks (DM) for write data • 1.8 V ± 0.1V VDD for [ –20/ –25/ –28] • 1.8 V ± 0.1V VDDQ for [ –20/ –25/ –28] • Posted CAS by programmable additive latency for better • DRAM or
6	HYB18T256161BF-28	Qimonda AG	256-Mbit x16 DDR2 SDRAM The 256-Mbit Double-Data-Rate-Two SDRAM offers the following key features: • Data masks (DM) for write data • 1.8 V ± 0.1V VDD for [ –20/ –25/ –28] • 1.8 V ± 0.1V VDDQ for [ –20/ –25/ –28] • Posted CAS by programmable additive latency for better • DRAM or
7	HYB18T512161B2F-20	Qimonda AG	512-Mbit x16 DDR2 SDRAM The 512-Mbit Double-Data-Rate-Two SDRAM offers the following key features: • Data masks (DM) for write data • 1.8 V ± 0.1V VDD for [ –20/ –25] • 1.8 V ± 0.1V VDDQ for [ –20/ –25] • Posted CAS by programmable additive latency for better • DRAM organizati
8	HYB18T512161B2F-25	Qimonda AG	512-Mbit x16 DDR2 SDRAM The 512-Mbit Double-Data-Rate-Two SDRAM offers the following key features: • Data masks (DM) for write data • 1.8 V ± 0.1V VDD for [ –20/ –25] • 1.8 V ± 0.1V VDDQ for [ –20/ –25] • Posted CAS by programmable additive latency for better • DRAM organizati
9	HYB18T512161BF	Qimonda AG	512-Mbit x16 DDR2 SDRAM The 512-Mbit Double-Data-Rate-Two SDRAM offers the following key features: • Commands entered on each positive clock edge, data and • 1.8 V ± 0.1V VDD for [ –25/ –28/ –33] • 2.0 V ± 0.1V VDD for [ –20/ –22] data mask are referenced to both edges of DQS •
10	HYB18H1G321AF-10	Qimonda AG	GDDR3 Graphics RAM 1-Gbit GDDR3 Graphics RAM • tWR programmable for Writes with Auto-Precharge • Data mask for write commands • Single ended READ strobe (RDQS) per byte. RDQS edgealigned with READ data • Single ended WRITE strobe (WDQS) per byte. WDQS center-aligned with WRITE data • DLL aligns
11	HYB18H1G321AF-11	Qimonda AG	GDDR3 Graphics RAM 1-Gbit GDDR3 Graphics RAM • tWR programmable for Writes with Auto-Precharge • Data mask for write commands • Single ended READ strobe (RDQS) per byte. RDQS edgealigned with READ data • Single ended WRITE strobe (WDQS) per byte. WDQS center-aligned with WRITE data • DLL aligns
12	HYB18H1G321AF-14	Qimonda AG	GDDR3 Graphics RAM 1-Gbit GDDR3 Graphics RAM • tWR programmable for Writes with Auto-Precharge • Data mask for write commands • Single ended READ strobe (RDQS) per byte. RDQS edgealigned with READ data • Single ended WRITE strobe (WDQS) per byte. WDQS center-aligned with WRITE data • DLL aligns
13	HYB18H256321BF-10	Qimonda AG	256-Mbit GDDR3 Graphics RAM GDDR3 Graphics RAM • Data mask for write commands • Single ended READ strobe (RDQS) per byte. RDQS edgealigned with READ data • Single ended WRITE strobe (WDQS) per byte. WDQS center-aligned with WRITE data • DLL aligns RDQS and DQ transitions with Clock • Programmable
14	HYB18H256321BF-11	Qimonda AG	256-Mbit GDDR3 Graphics RAM GDDR3 Graphics RAM • Data mask for write commands • Single ended READ strobe (RDQS) per byte. RDQS edgealigned with READ data • Single ended WRITE strobe (WDQS) per byte. WDQS center-aligned with WRITE data • DLL aligns RDQS and DQ transitions with Clock • Programmable
15	HYB18H256321BF-12	Qimonda AG	256-Mbit GDDR3 Graphics RAM GDDR3 Graphics RAM • Data mask for write commands • Single ended READ strobe (RDQS) per byte. RDQS edgealigned with READ data • Single ended WRITE strobe (WDQS) per byte. WDQS center-aligned with WRITE data • DLL aligns RDQS and DQ transitions with Clock • Programmable
16	HYB18H256321BF-14	Qimonda AG	256-Mbit GDDR3 Graphics RAM GDDR3 Graphics RAM • Data mask for write commands • Single ended READ strobe (RDQS) per byte. RDQS edgealigned with READ data • Single ended WRITE strobe (WDQS) per byte. WDQS center-aligned with WRITE data • DLL aligns RDQS and DQ transitions with Clock • Programmable
17	HYB18H512321BF-08	Qimonda AG	512-Mbit GDDR3 Graphics RAM • Data mask for write commands • Single ended READ strobe (RDQS) per byte. RDQS edgealigned with READ data • Single ended WRITE strobe (WDQS) per byte. WDQS center-aligned with WRITE data • DLL aligns RDQS and DQ transitions with Clock • Programmable
18	HYB18H512321BF-11	Qimonda AG	512-Mbit GDDR3 Graphics RAM • Data mask for write commands • Single ended READ strobe (RDQS) per byte. RDQS edgealigned with READ data • Single ended WRITE strobe (WDQS) per byte. WDQS center-aligned with WRITE data • DLL aligns RDQS and DQ transitions with Clock • Programmable
19	HYB18H512321BF-12	Qimonda AG	512-Mbit GDDR3 Graphics RAM • Data mask for write commands • Single ended READ strobe (RDQS) per byte. RDQS edgealigned with READ data • Single ended WRITE strobe (WDQS) per byte. WDQS center-aligned with WRITE data • DLL aligns RDQS and DQ transitions with Clock • Programmable
20	HYB18H512321BF-14	Qimonda AG	512-Mbit GDDR3 Graphics RAM • Data mask for write commands • Single ended READ strobe (RDQS) per byte. RDQS edgealigned with READ data • Single ended WRITE strobe (WDQS) per byte. WDQS center-aligned with WRITE data • DLL aligns RDQS and DQ transitions with Clock • Programmable