HYB18T512161B2F-20 |
Part Number | HYB18T512161B2F-20 |
Manufacturer | Qimonda AG |
Description | All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK falling). ... |
Features |
The 512-Mbit Double-Data-Rate-Two SDRAM offers the following key features: • Data masks (DM) for write data • 1.8 V ± 0.1V VDD for [ –20/ –25] • 1.8 V ± 0.1V VDDQ for [ –20/ –25] • Posted CAS by programmable additive latency for better • DRAM organizations with 16 data in/outputs command and data bus efficiency • Double Data Rate architecture: • Off-Chip-Driver impedance adjustment (OCD) and On – two data transfers per clock cycle Die-Termination (ODT) for better signal quality. – four internal banks for concurrent operation • Auto-Precharge operation for read and write bursts • Programmable CAS L... |
Document |
HYB18T512161B2F-20 Data Sheet
PDF 1.30MB |
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