| No. | parte # | Fabricante | Descripción | Hoja de Datos |
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Taiwan Semiconductor |
N-Channel Power MOSFET ● Pb-free plating ● RoHS compliant ● Halogen-free APPLICATIONS ● Lighting ● Charger ● Power Supply ● Switching applications TSM1NB60LCW Taiwan Semiconductor N-Channel Power MOSFET 600V, 0.55A, 15Ω PRODUCT SUMMARY PARAMETER VALUE VDS 600 RDS(o |
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ON Semiconductor |
2.5V / 3.3V Dual Channel Programmable Clock/Data Delay |
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ON Semiconductor |
Input to LVDS Fanout Buffer/Translator • Maximum Input Clock Frequency > 2.0 GHz • Maximum Input Data Rate > 2.5 Gb/s • 1 ps Maximum of RMS Clock Jitter • Typically 10 ps of Data Dependent Jitter • 380 ps Typical Propagation Delay • 120 ps Typical Rise and Fall Times • Functionally Compat |
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Dynex Semiconductor |
Rectifier Diode s Double Side Cooling s High Surge Capability KEY PARAMETERS VRRM IF(AV) IFSM 3600V 3019A 27000A APPLICATIONS s Rectification s Freewheel Diode s DC Motor Control s Power Supplies s Welding s Battery Chargers VOLTAGE RATINGS Type Number Repetitive |
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ON Semiconductor |
2.5V / 3.3V Differential 4:1 Mux To 1:2 CML Clock/Data Fanout / Translator • Differential CML Outputs, 400 mV Peak−to−Peak, • • • • • • Typical Operating Range: VCC = 2.375 V to 3.6 V with GND = 0 V Internal 50 W Input Termination Resistors VREFAC Reference Output QFN−32 Package, 5mm x 5mm 40°C to +85°C Ambient Operating T |
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ON Semiconductor |
2.5V / 3.3V Differential 4:1 Mux w/Input Equalizer to 1:2 CML Clock/Data Fanout / Translator 1 32 QFN32 MN SUFFIX CASE 488AM NB6L Q572M AWLYYWWG G A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping informati |
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ON Semiconductor |
2.5V / 3.3V Dual Channel Programmable Clock/Data Delay |
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Taiwan Semiconductor |
N-Channel Power MOSFET ● ● ● Low RDS(ON) 8Ω (Typ.) Low gate charge typical @ 6.1nC (Typ.) Low Crss typical @ 4.2pF (Typ.) Block Diagram Ordering Information Part No. TSM1NB60CH C5G TSM1NB60CP ROG Package TO-251 TO-252 Packing 75pcs / Tube 2.5Kpcs / 13” Reel 2.5Kpcs / 1 |
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Taiwan Semiconductor |
600V N-Channel Power MOSFET ● ● ● Low RDS(ON) 8Ω (Typ.) Low gate charge typical @ 6.1nC (Typ.) Low Crss typical @ 4.2pF (Typ.) Block Diagram Ordering Information Part No. TSM1NB60SCT B0 TSM1NB60SCT B0G TSM1NB60SCT A3 Package TO-92 TO-92 TO-92 Packing 1Kpcs / Bulk 1Kpcs / Bu |
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ON Semiconductor |
2.5V / 3.3V MULTILEVEL INPUT TO DIFFERENTIAL LVPECL/LVNECL o −3.465 V • Open Input Default State http://onsemi.com MARKING DIAGRAMS* 8 8 1 SO−8 D SUFFIX CASE 751 6L11 ALYW 1 8 8 1 TSSOP−8 DT SUFFIX CASE 948R A L Y W = Assembly Location = Wafer Lot = Year = Work Week 6L11 ALYW 1 • Q Outputs Will Default LOW |
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ON Semiconductor |
2.5V / 3.3V Any Differential Clock IN to Differential LVPECL OUT Clock Divider • Maximum Clock Input Frequency, 3.0 GHz • CLOCK Inputs Compatible with LVDS/LVPECL/CML/HSTL/HCSL • EN, MR, and SEL Inputs Compatible with LVTTL/LVCMOS • Rise/Fall Time 65 ps Typical • < 10 ps Typical Output−to−Output Skew • Example: 622.08 MHz Input |
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ON Semiconductor |
6GHz/6Gbps 2.5V/3.3V Multi-level Input to Differential Lvecl Clock or Data Translator/receiver/driver Buffer used, decouple VBB and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. • Maximum Input Clock Frequency w 6 GHz Typical • Maximum Input Data Rate Frequency w 6 Gb/s Typical • Low 12 |
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ON Semiconductor |
Differential CML Fanout Buffer • Maximum Input Clock Frequency > 4 GHz, Typical • 225 ps Typical Propagation Delay • 70 ps Typical Rise and Fall Times • 0.5 ps maximum RMS Clock Jitter • Differential CML Outputs, 380 mV peak−to−peak, typical • LVPECL Operating Range: VCC = 2.375 V |
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ON Semiconductor |
Differential 1:4 LVPECL Fanout Buffer • Input Clock Frequency > 3.0 GHz • Input Data Rate > 2.5 Gb/s • < 20 ps Within Device Output Skew • 350 ps Typical Propagation Delay • 150 ps Typical Rise and Fall Times • Differential LVPECL Outputs, 700 mV Amplitude, Typical • LVPECL Mode Operatin |
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ON Semiconductor |
Differential 1:4 CML Fanout Buffer A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. • • • • • • • • • • • Maximum Input Clock Frequency |
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ON Semiconductor |
Differential LVPECL Clock / Data Fanout Buffer • Input Clock Frequency > 4.0 GHz • 280 ps Typical Propagation Delay • 100 ps Typical Rise and Fall Times • 0.5 ps maximum RMS Clock Jitter • Differential LVPECL Outputs, 780 mV Amplitude, typical • LVPECL Operating Range: VCC = 2.375 V to 3.63 V wit |
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ON Semiconductor |
Differential 2 X 2 Crosspoint Switch •ăInput Clock Frequency > 3.0GHz •ăInput Data Rate > 3 Gb/s •ă425 ps Typical Propagation Delay •ă100 ps Typical Rise and Fall Times •ă0.5 ps maximum RMS Clock Jitter •ăLVPECL, CML or LVDS Input Compatible •ăDifferential LVPECL Outputs, 800 mV Amplitu |
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ON Semiconductor |
Differential 2 x 2 Crosspoint Switch •ăInput Clock Frequency > 3.0 GHz •ăInput Data Rate > 3 Gb/s •ă360 ps Typical Propagation Delay •ă65 ps Typical Rise and Fall Times •ăDifferential CML Outputs, 380 mV peak-to-peak, typical •ăOperating Range: VCC = 2.375 V to 3.63 V with GND = 0 V •ăI |
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ON Semiconductor |
Input to LVDS Fanout Buffer/Translator • Input Clock Frequency > 2.0 GHz • Input Data Rate > 2.5 Gb/s • RMS Clock Jitter −0.5 ps, Typical • 622 Mb/s Data Dependent Jitter − 6 ps, Typical • 380 ps Typical Propagation Delay • 120 ps Typical Rise and Fall Times • Single Power Supply; VCC = 2 |
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ON Semiconductor |
Differential Input to LVDS Fanout Buffer/Translator • Maximum Input Clock Frequency > 2.0 GHz • Maximum Input Data Rate > 2.5 Gb/s • 1 ps Maximum RMS Clock Jitter • Typically 10 ps Data Dependent Jitter • 380 ps Typical Propagation Delay • 120 ps Typical Rise and Fall Times • VREF_AC Reference Output |
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Desde 2024. D4U Semiconductor.
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