NXP BD1 Hoja de datos

No.	parte #	Fabricante	Descripción
1	BD131	NXP	NPN power transistor • High current (max. 3 A) • Low voltage (max. 45 V). APPLICATIONS • General purpose power applications. DESCRIPTION handbook, halfpage BD131 PINNING PIN 1 2 3 emitter collector, connected to metal part of mounting surface base DESCRIPTION NPN power
2	BD136	NXP	PNP power transistors • High current (max. 1.5 A) • Low voltage (max. 80 V). APPLICATIONS • General purpose power applications, e.g. driver stages in hi-fi amplifiers and television circuits. DESCRIPTION PNP power transistor in a TO-126; SOT32 plastic package. NPN complem
3	PDIUSBD11D	NXP	USB device with serial interface • Complies with the Universal Serial Bus specification Rev. 1.1 • Complies with the ACPI, OnNOW, and USB power management requirements DESCRIPTION The Universal Serial Bus hub PDIUSBD11 is a cost and feature-optimized USB interface device. It is us
4	LPC1518JBD100	NXP Semiconductors	32-bit ARM Cortex-M3 microcontroller and a higher level of support block integration. The LPC15xx operate at CPU frequencies of up to 72 MHz. The ARM Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with separate local instruction and data buses as well as a
5	PDUSBD12PWDH	NXP	nullUSB interface device with parallel bus • Complies with the Universal Serial Bus specification Rev. 1.1 • High performance USB interface device with integrated SIE, FIFO memory, transceiver and voltage regulator DESCRIPTION The PDIUSBD12 is a cost and feature-optimized USB device. It is
6	LPC1820FBD144	NXP	32-bit ARM Cortex-M3 flashless MCU and a high level of support block integration. The LPC1850/30/20/10 operate at CPU frequencies of up to 180 MHz. The ARM Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with separate local instruction and data buses as
7	PDIUSBD11	NXP	USB device with serial interface • Complies with the Universal Serial Bus specification Rev. 1.1 • Complies with the ACPI, OnNOW, and USB power management requirements DESCRIPTION The Universal Serial Bus hub PDIUSBD11 is a cost and feature-optimized USB interface device. It is us
8	PDIUSBD12	NXP	USB interface device like SoftConnect™, GoodLink™, programmable clock output, low frequency crystal oscillator, and integration of termination resistors. All of these features contribute to signiﬁcant cost savings in the system implementation and at the same time ease th
9	LPC1823JBD144	NXP	32-bit ARM Cortex-M3 MCU and a high level of support block integration. The LPC185x/3x/2x/1x operate at CPU frequencies of up to 180 MHz. The ARM Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with separate local instruction and data buses as
10	PDIUSBD11N	NXP	USB device with serial interface • Complies with the Universal Serial Bus specification Rev. 1.1 • Complies with the ACPI, OnNOW, and USB power management requirements DESCRIPTION The Universal Serial Bus hub PDIUSBD11 is a cost and feature-optimized USB interface device. It is us
11	PDIUSBD12D	NXP	nullUSB interface device with parallel bus • Complies with the Universal Serial Bus specification Rev. 1.1 • High performance USB interface device with integrated SIE, FIFO memory, transceiver and voltage regulator DESCRIPTION The PDIUSBD12 is a cost and feature-optimized USB device. It is
12	PDIUSBD12PW	NXP	nullUSB interface device with parallel bus • Complies with the Universal Serial Bus specification Rev. 1.1 • High performance USB interface device with integrated SIE, FIFO memory, transceiver and voltage regulator DESCRIPTION The PDIUSBD12 is a cost and feature-optimized USB device. It is
13	LPC1822JBD144	NXP	32-bit ARM Cortex-M3 MCU and a high level of support block integration. The LPC185x/3x/2x/1x operate at CPU frequencies of up to 180 MHz. The ARM Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with separate local instruction and data buses as
14	LPC1519JBD100	NXP Semiconductors	32-bit ARM Cortex-M3 microcontroller and a higher level of support block integration. The LPC15xx operate at CPU frequencies of up to 72 MHz. The ARM Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with separate local instruction and data buses as well as a
15	LPC1837JBD144	NXP	32-bit ARM Cortex-M3 MCU and a high level of support block integration. The LPC185x/3x/2x/1x operate at CPU frequencies of up to 180 MHz. The ARM Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with separate local instruction and data buses as
16	LPC1833JBD144	NXP	32-bit ARM Cortex-M3 MCU and a high level of support block integration. The LPC185x/3x/2x/1x operate at CPU frequencies of up to 180 MHz. The ARM Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with separate local instruction and data buses as
17	LPC1825JBD144	NXP	32-bit ARM Cortex-M3 MCU and a high level of support block integration. The LPC185x/3x/2x/1x operate at CPU frequencies of up to 180 MHz. The ARM Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with separate local instruction and data buses as
18	LPC1815JBD144	NXP	32-bit ARM Cortex-M3 MCU and a high level of support block integration. The LPC185x/3x/2x/1x operate at CPU frequencies of up to 180 MHz. The ARM Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with separate local instruction and data buses as
19	LPC1549JBD100	NXP Semiconductors	32-bit ARM Cortex-M3 microcontroller and a higher level of support block integration. The LPC15xx operate at CPU frequencies of up to 72 MHz. The ARM Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with separate local instruction and data buses as well as a
20	LPC1548JBD100	NXP Semiconductors	32-bit ARM Cortex-M3 microcontroller and a higher level of support block integration. The LPC15xx operate at CPU frequencies of up to 72 MHz. The ARM Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with separate local instruction and data buses as well as a