| No. | parte # | Fabricante | Descripción | Hoja de Datos |
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Hitachi Semiconductor |
Hex D-Type Flip-Flop with Master Reset • Outputs Source/Sink 24 mA Pin Arrangement MR 1 Q0 2 D0 3 D1 4 Q1 5 D2 6 Q2 7 GND 8 (Top view) 16 VCC 15 Q5 14 D5 13 D4 12 Q4 11 D3 10 Q3 9 CP HD74AC174 Logic Symbol D0 D1 D2 CP MR D3 D4 D5 Q0 Q1 Q2 Q3 Q4 Q5 Pin Names D0 to D5 CP MR Q0 to Q5 |
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Hitachi Semiconductor |
Dual 1-of-4 Decoder/Demultiplexer • • • • • Multifunction Capability Two Completely Independent 1-of-4 Decoders Active Low Mutually Exclusive Outputs Outputs Source/Sink 24 mA HD74ACT139 has TTL-Compatible Inputs HD74AC139/HD74ACT139 Pin Arrangement Ea 1 A0a 2 A1a 3 O0a 4 O1a 5 O2a |
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Hitachi Semiconductor |
8-bit Shift Register • Outputs Source/Sink 24 mA • HD74ACT166 has TTL-Compatible Inputs Pin Arrangement DS 1 P0 2 P1 3 P2 4 P3 5 CP2 6 CP1 7 GND 8 (Top view) 16 VCC 15 PE 14 P7 13 Q7 12 P6 11 P5 10 P4 9 MR HD74AC166/HD74ACT166 Logic Symbol 15 2 3 4 5 10 11 12 14 PE |
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Hitachi Semiconductor |
8-bit Addressable Latch • • • • • • • Serial-to-Parallel Conversion Eight Bits of Storage with Output of Each Bit Available Random (Addressable) Data Entry Active High Demultiplexing or Decoding Capability Easily Expandable Common Clear Outputs Source/Sink 24 mA HD74AC259 |
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Hitachi Semiconductor |
4 x 4 Register File with 3-State Output |
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Hitachi Semiconductor |
Octal Buffer/Line Driver with 3-State Output • 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers • Outputs Source/Sink 24 mA • HD74ACT244 has TTL-Compatible Inputs Pin Arrangement OE1 1 2 3 4 5 6 7 8 9 GND 10 (Top view) 20 VCC 19 OE2 18 17 16 15 14 13 12 11 HD74AC244/HD74AC |
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Hitachi Semiconductor |
Serial-In/ Parallel-Out Shift Register an asynchronous Master Reset which clears the register, setting all outputs Low independent of the clock. Features • Outputs Source/Sink 24 mA • HD74ACT164 has TTL-Compatible Inputs Pin Arrangement A 1 B 2 Q0 3 Q1 4 Q2 5 Q3 6 GND 7 (Top view) 14 |
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Hitachi Semiconductor |
Octal Buffer/Line Driver with 3-State Output • 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers • Outputs Source/Sink 24 mA • HD74ACT240 has TTL-Compatible Inputs Pin Arrangement OE1 1 2 3 4 5 6 7 8 9 GND 10 (Top view) 20 VCC 19 OE2 18 17 16 15 14 13 12 11 HD74AC240/HD74AC |
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Hitachi Semiconductor |
9-bit Parity Generator/Checker • Outputs Source/Sink 24 mA • HD74ACT280 has TTL-Cmpatible Inputs Pin Arrangement I6 1 I7 2 NC 3 I8 4 ΣE 5 ΣO 6 GND 7 (Top view) 14 VCC 13 I5 12 I4 11 I3 10 I2 9 I1 8 I0 HD74AC280/HD74ACT280 Logic Symbol I0 I1 I2 I3 I4 I5 I6 I7 I8 ΣO Σ |
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Hitachi Semiconductor |
Dual 1-of-4 Decoder/Demultiplexer • • • • • Multifunction Capability Two Completely Independent 1-of-4 Decoders Active Low Mutually Exclusive Outputs Outputs Source/Sink 24 mA HD74ACT139 has TTL-Compatible Inputs HD74AC139/HD74ACT139 Pin Arrangement Ea 1 A0a 2 A1a 3 O0a 4 O1a 5 O2a |
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Hitachi Semiconductor |
Quad 2-Input NOR Gate • Outputs Source/Sink 24 mA Pin Arrangement 1 2 3 4 5 6 GND 7 (Top view) 14 VCC 13 12 11 10 9 8 DC Characteristics (unless otherwise specified) Item Maximum quiescent supply current Maximum quiescent supply current Symbol I CC I CC Max 40 4.0 Uni |
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Hitachi Semiconductor |
Quad Buffer/Line Driver with 3-State Output • 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers • Outputs Source/Sink 24 mA • HD74ACT126 has TTL-Compatible Inputs Pin Arrangement E 1 D 2 O 3 E 4 D 5 O 6 GND 7 (Top view) 14 VCC 13 E 12 D 11 O 10 E 9 D 8 O HD74AC126/HD74ACT1 |
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Hitachi Semiconductor |
4-bit Parallel-Access Shift Register parallel inputs, parallel outputs, J-K serial inputs, Shift/Load control input, and a direct overriding clear. This shift register can operate in two modes: Parallel load; Shift from Q 0 towards Q3. Parallel loading is accomplished by applying the fo |
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Hitachi Semiconductor |
Hex Inverter Buffer with 3-State Output • 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers • Outputs Source/Sink 24 mA • HD74ACT368 has TTL-Compatible Inputs Pin Arrangement OE1 I O I O I O GND 1 2 3 4 5 6 7 8 (Top view) 16 VCC 15 OE2 14 I 13 O 12 I 11 O 10 I 9 O HD7 |
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Hitachi Semiconductor |
Octal Transparent Latch with 3-State Output • • • • Eight Latches in a Single Package 3-State Outputs for Bus Interfacing Outputs Source/Sink 24 mA HD74AC373 has TTL-Compatible Inputs HD74AC373/HD74ACT373 Pin Arrangement OE 1 O0 2 D0 3 D1 4 O1 5 O2 6 D2 7 D3 8 O3 9 Gnd 10 (Top view) 20 VCC |
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Hitachi Semiconductor |
Dual JK Flip-Flop (with Separate Clear and Clock) • Outputs Source/Sink 24 mA • HD74ACT107 has TTL-Compatible Inputs Pin Arrangement J1 1 Q1 2 Q1 3 K1 4 Q2 5 Q2 6 GND 7 (Top view) 14 VCC 13 CD1 12 CP1 11 K2 10 CD2 9 CP2 8 J2 HD74AC107/HD74ACT107 Logic Symbol 3 8 9 Q1 2 11 1 12 4 J1 CP1 K1 Q1 |
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Hitachi Semiconductor |
Dual JK Negative Edge-Triggered Flip-Flop individual J, K, Clock and asynchronous Set and Clear inputs to each flip-flop. When the clock goes High, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may change when the clock is High and the bistable will |
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Hitachi Semiconductor |
Quad Buffer/Line Driver with 3-State Output • 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers • Outputs Source/Sink 24 mA • HD74ACT126 has TTL-Compatible Inputs Pin Arrangement E 1 D 2 O 3 E 4 D 5 O 6 GND 7 (Top view) 14 VCC 13 E 12 D 11 O 10 E 9 D 8 O HD74AC126/HD74ACT1 |
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Hitachi Semiconductor |
1-of-8 Decoder/Demultiplexer • • • • • Demultiplexing Capability Multiple Input Enable for Easy Expansion Active LOW Mutually Exclusive Outputs Outputs Source/Sink 24 mA HD74ACT138 has TTL-Compatible Inputs HD74AC138/HD74ACT138 Pin Arrangement A0 1 A1 2 A2 3 E1 4 E2 5 E3 6 O7 |
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Hitachi Semiconductor |
8-bit Shift Register • Outputs Source/Sink 24 mA • HD74ACT166 has TTL-Compatible Inputs Pin Arrangement DS 1 P0 2 P1 3 P2 4 P3 5 CP2 6 CP1 7 GND 8 (Top view) 16 VCC 15 PE 14 P7 13 Q7 12 P6 11 P5 10 P4 9 MR HD74AC166/HD74ACT166 Logic Symbol 15 2 3 4 5 10 11 12 14 PE |
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Desde 2024. D4U Semiconductor.
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