No. | parte # | Fabricante | Descripción | Hoja de Datos |
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ETC |
3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility -3.3V and 5.0V operation with low standby power -I/O pin-compatibility between different devices in the same packages -PCI compliant (at 5.0V), full speed 33 MHz implementations -High design security provided by security fuses QL2009 Block Diagram 6 |
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ETC |
3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility -3.3V and 5.0V operation with low standby power -I/O pin-compatibility between different devices in the same packages -PCI compliant (at 5.0V), full speed 33 MHz implementations -High design security provided by security fuses QL2009 Block Diagram 6 |
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ETC |
3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility -3.3V and 5.0V operation with low standby power -I/O pin-compatibility between different devices in the same packages -PCI compliant (at 5.0V), full speed 33 MHz implementations -High design security provided by security fuses QL2009 Block Diagram 6 |
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ETC |
3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility -3.3V and 5.0V operation with low standby power -I/O pin-compatibility between different devices in the same packages -PCI compliant (at 5.0V), full speed 33 MHz implementations -High design security provided by security fuses QL2009 Block Diagram 6 |
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ETC |
3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility -3.3V and 5.0V operation with low standby power -I/O pin-compatibility between different devices in the same packages -PCI compliant (at 5.0V), full speed 33 MHz implementations -High design security provided by security fuses QL2009 Block Diagram 6 |
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ETC |
3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility -3.3V and 5.0V operation with low standby power -I/O pin-compatibility between different devices in the same packages -PCI compliant (at 5.0V), full speed 33 MHz implementations -High design security provided by security fuses QL2009 Block Diagram 6 |
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|
ETC |
3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility -3.3V and 5.0V operation with low standby power -I/O pin-compatibility between different devices in the same packages -PCI compliant (at 5.0V), full speed 33 MHz implementations -High design security provided by security fuses QL2009 Block Diagram 6 |
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|
|
ETC |
3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility -3.3V and 5.0V operation with low standby power -I/O pin-compatibility between different devices in the same packages -PCI compliant (at 5.0V), full speed 33 MHz implementations -High design security provided by security fuses QL2009 Block Diagram 6 |
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|
|
ETC |
3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility -3.3V and 5.0V operation with low standby power -I/O pin-compatibility between different devices in the same packages -PCI compliant (at 5.0V), full speed 33 MHz implementations -High design security provided by security fuses QL2009 Block Diagram 6 |
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|
|
ETC |
3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility -3.3V and 5.0V operation with low standby power -I/O pin-compatibility between different devices in the same packages -PCI compliant (at 5.0V), full speed 33 MHz implementations -High design security provided by security fuses QL2009 Block Diagram 6 |
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|
|
ETC |
3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility -3.3V and 5.0V operation with low standby power -I/O pin-compatibility between different devices in the same packages -PCI compliant (at 5.0V), full speed 33 MHz implementations -High design security provided by security fuses QL2009 Block Diagram 6 |
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|
|
ETC |
3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility -3.3V and 5.0V operation with low standby power -I/O pin-compatibility between different devices in the same packages -PCI compliant (at 5.0V), full speed 33 MHz implementations -High design security provided by security fuses QL2009 Block Diagram 6 |
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|
|
ETC |
3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility -3.3V and 5.0V operation with low standby power -I/O pin-compatibility between different devices in the same packages -PCI compliant (at 5.0V), full speed 33 MHz implementations -High design security provided by security fuses QL2009 Block Diagram 6 |
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|
|
ETC |
3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility -3.3V and 5.0V operation with low standby power -I/O pin-compatibility between different devices in the same packages -PCI compliant (at 5.0V), full speed 33 MHz implementations -High design security provided by security fuses QL2009 Block Diagram 6 |
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|
ETC |
3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility -3.3V and 5.0V operation with low standby power -I/O pin-compatibility between different devices in the same packages -PCI compliant (at 5.0V), full speed 33 MHz implementations -High design security provided by security fuses QL2009 Block Diagram 6 |
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ETC |
3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility -3.3V and 5.0V operation with low standby power -I/O pin-compatibility between different devices in the same packages -PCI compliant (at 5.0V), full speed 33 MHz implementations -High design security provided by security fuses QL2009 Block Diagram 6 |
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|
|
ETC |
3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility -3.3V and 5.0V operation with low standby power -I/O pin-compatibility between different devices in the same packages -PCI compliant (at 5.0V), full speed 33 MHz implementations -High design security provided by security fuses QL2009 Block Diagram 6 |
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|
|
ETC |
3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility -3.3V and 5.0V operation with low standby power -I/O pin-compatibility between different devices in the same packages -PCI compliant (at 5.0V), full speed 33 MHz implementations -High design security provided by security fuses QL2009 Block Diagram 6 |
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|
|
ETC |
3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility -3.3V and 5.0V operation with low standby power -I/O pin-compatibility between different devices in the same packages -PCI compliant (at 5.0V), full speed 33 MHz implementations -High design security provided by security fuses QL2009 Block Diagram 6 |
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|
|
ETC |
3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility -3.3V and 5.0V operation with low standby power -I/O pin-compatibility between different devices in the same packages -PCI compliant (at 5.0V), full speed 33 MHz implementations -High design security provided by security fuses QL2009 Block Diagram 6 |
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