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Texas Instruments |
Memory Power Solution Synchronous Buck Controller 1 •2 Synchronous Buck Controller (VDDQ) – Conversion Voltage Range: 3 V to 28 V – Output Voltage Range: 0.7 V to 1.8 V – 0.8% VREF Accuracy – D-CAP™ Mode for Fast Transient Response – Selectable 300 kHz/400 kHz Switching Frequencies – Optimized Effic |
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ETC |
64Kb FRAM Serial Memory 64K bit Ferroelectric Nonvolatile RAM • Organized as 8,192 x 8 bits • High Endurance 1 Trillion (1012) Read/Writes • 10 Year Data Retention • NoDelay™ Writes • Advanced high-reliability ferroelectric process Very Fast Serial Peripheral Interface - SP |
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Texas Instruments |
FLASH MEMORIES of Program/Erase Cycle Completion – Hardware Method for Detection of Program/Erase Cycle Completion Through Ready/Busy (RY/BY) Output Pin "D High-Speed Data Access at 5-V VCC 10% at Three Temperature Ranges – 80 ns Commercial . . . 0°C to 70°C – 90 n |
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Texas Instruments |
DYNAMIC RANDOM-ACCESS MEMORIES maximum RAS access times of 40, 50, and 60 ns. All inputs and outputs, including clocks, are compatible with LVTTL. All addresses and data-in lines are latched on chip to simplify system design. Data out is unlatched to allow greater system flexibili |
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Texas Instruments |
256-BITS PROGRAMMABLE READ-ONLY MEMORIES 024 PACKAGING INFORMATION Orderable Device JBP18S030MJ Status Package Type Package Pins Package Eco Plan (1) Drawing Qty (2) NRND CDIP J 16 25 Non-RoHS & Green Lead finish/ Ball material (6) SNPB MSL Peak Temp Op Temp (°C) (3) N / A f |
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ETC |
2048-word x 9-bit CMOS Parallel In-Out FIFO Memory • • • • • • • • • • First-in, first-out dual port memory 2 k × 9 organization Low-power CMOS 1.3 micron technology Asynchronous and simultaneous read and write Fully expandable in depth and/or width Single 5 V power supply Empty and full warning flag |
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Texas Instruments |
FLASH MEMORIES of Program/Erase Cycle Completion – Hardware Method for Detection of Program/Erase Cycle Completion Through Ready/Busy (RY/BY) Output Pin "D High-Speed Data Access at 3.3-V VCC 10% at Three Temperature Ranges – 90 ns Commercial . . . 0°C to 70°C – 10 |
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Texas Instruments |
65536 BY 8-BIT FLASH MEMORY n in temperature ranges of 0°C to 70°C (FML suffix), – 40°C to 85°C ( FME suffix), and – 40°C to 125°C ( FMQ suffix). TMS28F512A 65536 BY 8-BIT FLASH MEMORY SMJS514C – FEBRUARY 1994 – REVISED AUGUST 1997 FM PACKAGE ( TOP VIEW ) A12 A15 NC VPP VCC W |
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Texas Instruments |
DYNAMIC RANDOM-ACCESS MEMORIES maximum RAS access times of 60 ns, 70 ns and 80 ns. Maximum power consumption is as low as 385 mW operating and 6 mW standby. All inputs and outputs, including clocks, are compatible with Series 74 TTL. All addresses and data-in lines are latched |
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Texas Instruments |
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY ce D Power-Down Mode D Compatible With JEDEC Standards D 16K RAS-Only Refresh (Total for All Banks) D 4K Auto Refresh (Total for All Banks)/64 ms D Automatic Precharge and Controlled Precharge D Burst Interruptions Supported: – Read Interruption – Wr |
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ETC |
NPN SILICON ANNULAR MEMORY DRIVER TRANSISTOR |
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ETC |
USB Multiple Slots Flash Memory Card Reader Controller TRM ………………………………………………………………….. 1 Application Block Diagram…………………………………………………… 3 Pin Assignment…………………………………………………………………. 5 System Architecture and Reference Design………………………………. 9 4.1 AU9360 Block Diagram…………………………………………………… 9 4.2 Sample Schematics…………… |
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ETC |
4 MEG x 16 EDO DRAM • Single +3.3V ±0.3V power supply • Industry-standard x16 pinout, timing, functions, and package • 12 row, 10 column addresses (4) 13 row, 9 column addresses (8) • High-performance CMOS silicon-gate process • All inputs, outputs and clocks are LVTTL- |
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ETC |
NON-VOLATILE MEMORY/NON-VOLATILE RAM |
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ETC |
CMOS Video JOG Memory Control 7 IDEC1_HD IDEC1_VD IDEC1_CF IDEC1_PR PIN No. 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 I/O — I I I I I I I — — — O O O O O O O O O O O O — O O O O — O O O O O O — — |
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Texas Instruments |
DYNAMIC RANDOM-ACCESS MEMORIES maximum RAS access times of 50, 60, and 70 ns. All address and data-in lines are latched on chip to simplify system design. Data out is unlatched to allow greater system flexibility. DJ/DGA PACKAGES ( TOP VIEW ) VCC DQ1 DQ2 W RAS A11† 1 2 3 4 5 6 |
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Texas Instruments |
Memory Power Solution Synchronous Buck Controller •1 Synchronous Buck Controller (VDDQ) – Conversion Voltage Range: 3 to 28 V – Output Voltage Range: 0.7 to 1.8 V – 0.8% VREF Accuracy – D-CAP™ Mode for Fast Transient Response – Selectable 300-kHz/400-kHz Switching Frequencies – Optimized Efficiency |
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ETC |
64BIT RANDOM ACCESS MEMORY |
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ETC |
8MEGABIT (1M8 /512K16) 3 VOLT CMOS FLASH MEMERY • Single 3.0 V read, program, and erase Minimizes system level power requirements • Compatible with JEDEC-standard commands 2 Uses same software commands as E PROMs • Compatible with JEDEC-standard world-wide pinouts 48-pin TSOP(I) • Minimum 100,000 |
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ETC |
64Kb Bytewide FRAM Memory 64K bit Ferroelectric Nonvolatile RAM • Organized as 8,192 x 8 bits • High endurance 10 Billion (1010) read/writes • 10 year data retention at 85° C • NoDelay™ write • Advanced high-reliability ferroelectric process Superior to BBSRAM Modules • No ba |
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Desde 2024. D4U Semiconductor.
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