No. | parte # | Fabricante | Descripción | Hoja de Datos |
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Alliance Semiconductor Corporation |
(AS7C33128NTF32B / AS7C33128NTF36B) 3.3V 128K x 32/36 Flowthrough Synchronous SRAM • Organization: 131,072 words × 32 or 36 bits • NTD™architecture for efficient bus operation • Fast clock to data access: 7.5/8.0/10.0 ns • Fast OE access time: 3.5/4.0 ns • Fully synchronous operation • Flow-through mode • Asynchronous output enable |
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Alliance Semiconductor Corporation |
Peak Reducing EMI Solution • Generates an EMI optimized clocking • • • • • • signal at the output. Selectable output frequency range. Single 1.25% or 2.4% down spread output. Integrated loop filter components. Operates with a 3.3V supply. Low-power CMOS design. Available in 8- |
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Alliance Semiconductor Corporation |
Low Frequency EMI Reduction FCC approved method of EMI attenuation. Generates a low EMI spread spectrum of the input clock frequency. Optimized for input frequency range between 35MHz – 55MHz. Internal loop filter minimizes external components and board space. Frequency Deviati |
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Alliance Semiconductor Corporation |
Low Power EMI Reduction IC FCC approved method of EMI attenuation. Provides up to 15dB EMI reduction. Generates a 4X REF EMI spread output Spectrum clock of the input frequency. Optimized for input frequency range from 10 to 20MHz. External Loop Filter for configur |
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Alliance Semiconductor Corporation |
3.3V 128Kx18 Pipelined SRAM • Organization: 131,072 words × 18 bits • NTD™ architecture for efficient bus operation • Fast clock speeds to 200 MHz • Fast clock to data access: 3.0/3.5/4.0 ns • Fast OE access time: 3.0/3.5/4.0 ns • Fully synchronous operation • Asynchronous outp |
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Alliance Semiconductor Corporation |
(AS7C33128PFD32A / AS7C33128PFD36A) 3.3V 128K X 32/36 pipeline burst synchronous SRAM • Organization: 131,072 words × 32 or 36 bits • Fast clock speeds to 166 MHz in LVTTL/LVCMOS • Fast clock to data access: 3.5/3.8/4.0/5.0 ns • Fast OE access time: 3.5/3.8/4.0/5.0 ns • Fully synchronous register-to-register operation • Single registe |
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Alliance Semiconductor Corporation |
3.3V 2M x 18 Pipelined SRAM • Organization: 2,097,152 words × 18 bits • NTD™ architecture for efficient bus operation • Fast clock speeds to 200 MHz • Fast clock to data access: 3.2/3.5/3.8 ns • Fast OE access time: 3.2/3.5/3.8 ns • Fully synchronous operation • Common data inp |
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Alliance Semiconductor Corporation |
(ASM5P23S05A / ASM5P23S09A) 3.3V SpreadTrak Zero Delay Buffer 15 MHz to 133 MHz operating range, compatible with CPU and PCI bus frequencies. Zero input - output propagation delay. Multiple low-skew outputs. Output-output skew less than 250 pS. Device-device skew less than 700 pS. One input drives 9 outputs, gr |
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Alliance Semiconductor Corporation |
Peak EMI Reducing Solution Generates an EMI optimized clock signal at output. Input frequency: 25 MHz. Frequency outputs: o o USB Clock (48 MHz unmodulated) 50 MHz (modulated), ±1% centre spread shielding that are required to pass EMI regulations. The ASM3P2853A modulates the |
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Alliance Semiconductor Corporation |
Low Power EMI Reduction IC FCC approved method of EMI attenuation. Generates a 1X low EMI spread spectrum clock of the input frequency. Input frequency range: 20MHz –34MHz. Internal loop filter minimizes external components and board space. Frequency deviation: -1.5% Low inher |
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Alliance Semiconductor Corporation |
5V 128K x 8 CMOS SRAM • Industrial and commercial temperatures • Organization: 131,072 x 8 bits • High speed - 10/12/15/20 ns address access time - 5/6/7/8 ns output enable access time • Low power consumption: ACTIVE - 605mW / max @ 10 ns • Low power consumption: STANDBY |
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Alliance Semiconductor Corporation |
2.5V LCD Panel Reduction § § § § § § § § § § § § § L2042A cost savings by reducing the number of circuit board layers ferrite beads, shielding and other passive components that are traditionally required to pass EMI regulations. The L2042A uses the most efficient and optim |
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Alliance Semiconductor Corporation |
(ASM809 / ASM810) 3 Pin Microcontroller Power Supply Supervisor • • • • • • Monitor 5V, 3.3V and 3V supplies 140ms min. reset pulse width Active-low reset valid with 1.1V supply (ASM809) Small 3-pin SOT-23 package No external components Specified over full temperature range - -40°C to 105°C Applications • • • • |
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Alliance Semiconductor Corporation |
(ASM809 / ASM810) 3 Pin Microcontroller Power Supply Supervisor • • • • • • Monitor 5V, 3.3V and 3V supplies 140ms min. reset pulse width Active-low reset valid with 1.1V supply (ASM809) Small 3-pin SOT-23 package No external components Specified over full temperature range - -40°C to 105°C Applications • • • • |
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Alliance Semiconductor Corporation |
(AS7C33128FT32B / AS7C33128FT36B) 3.3V 128K x 32/36 Flow Through Synchronous SRAM • • • • • • • Organization: 131,072 words × 32 or 36 bits Fast clock to data access: 6.5/7.5/8.0/10.0 ns Fast OE access time: 3.5/4.0 ns Fully synchronous flow through operation Asynchronous output enable control Available in 100-pin TQFP package Ind |
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Alliance Semiconductor Corporation |
3.3V 128K x 18 Flowthrough Synchronous SRAM • • • • • • • • Organization: 131,072 words × 18 bits NTD™ architecture for efficient bus operation Fast clock to data access: 7.5/8.0/10.0 ns Fast OE access time: 3.5/4.0 ns Fully synchronous operation Flow-through mode Asynchronous output enable co |
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Alliance Semiconductor Corporation |
(AS7C33128NTF32B / AS7C33128NTF36B) 3.3V 128K x 32/36 Flowthrough Synchronous SRAM • Organization: 131,072 words × 32 or 36 bits • NTD™architecture for efficient bus operation • Fast clock to data access: 7.5/8.0/10.0 ns • Fast OE access time: 3.5/4.0 ns • Fully synchronous operation • Flow-through mode • Asynchronous output enable |
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Alliance Semiconductor Corporation |
3.3V 128K x 18 pipeline burst synchronous SRAM • Organization: 131,072 words × 18 bits • Fast clock speeds to 200 MHz • Fast clock to data access: 3.0/3.5/4.0 ns • Fast OE access time: 3.0/3.5/4.0 ns • Fully synchronous register-to-register operation • Double-cycle deselect • Asynchronous output |
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Alliance Semiconductor Corporation |
(AS7C33128PFD32B / AS7C33128PFD36B) 3.3V 128K X 32/36 pipeline burst synchronous SRAM • Organization: 131,072 words × 32 or 36 bits • Fast clock speeds to 200 MHz • Fast clock to data access: 3.0/3.5/4.0 ns • Fast OE access time: 3.0/3.5/4.0 ns • Fully synchronous register-to-register operation • Double-cycle deselect • Asynchronous o |
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Alliance Semiconductor Corporation |
(AS7C33128PFS32A / AS7C33128PFS36A) 3.3V 128K X 32/36 pipeline burst synchronous SRAM • Organization: 131,072 words × 32 or 36 bits • Fast clock speeds to 200 MHz in LVTTL/LVCMOS • Fast clock to data access: 3.0/3.1/3.5/4.0/5.0 ns • Fast OE access time: 3.0/3.1/3.5/4.0/5.0 ns • Fully synchronous register-to-register operation • Single |
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