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AS7C33128NTD18B |
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| Part Number | AS7C33128NTD18B |
| Manufacturer | Alliance Semiconductor Corporation |
| Description | The AS7C33128NTD18B family is a high performance CMOS 2 Mbit synchronous Static Random Access Memory (SRAM) organized as 131,072 words × 18 bits and incorporates a LATE LATE Write. This variation of t... |
| Features |
• Organization: 131,072 words × 18 bits • NTD™ architecture for efficient bus operation • Fast clock speeds to 200 MHz • Fast clock to data access: 3.0/3.5/4.0 ns • Fast OE access time: 3.0/3.5/4.0 ns • Fully synchronous operation • Asynchronous output enable control • Available in 100-pin TQFP package www.DataSheet4U.com • Byte write enables • Clock enable for operation hold Logic block diagram A[16:0] 17 D • Multiple chip enables for easy expansion • 3.3V core power supply • 2.5V or 3.3V I/O operation with separate VDDQ • Self-timed write cycles • Interleaved or linear burst modes • Snooze ... |
| Document |
 AS7C33128NTD18B Data Sheet
PDF 489.68KB |
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| 2 | AS7C33128NTD32B |
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(AS7C33128NTD32B / AS7C33128NTD36B) 3.3V 128Kx32/36 Pipelined SRAM |
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| 3 | AS7C33128NTD36A |
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| 4 | AS7C33128NTD36B |
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(AS7C33128NTD32B / AS7C33128NTD36B) 3.3V 128Kx32/36 Pipelined SRAM |
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| 5 | AS7C33128NTF18B |
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| 6 | AS7C33128NTF32B |
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Desde 2024. D4U Semiconductor.
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