| No. | parte # | Fabricante | Descripción | Hoja de Datos |
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Alliance Semiconductor |
5V 64K x 16 CMOS SRAM • JEDEC standard packaging • ESD protection > _ 2000 volts - 44-pin 400 mil SOJ - 44-pin TSOP 2-400 Pin arrangement 44-Pin SOJ (400 mil), TSOP 2 A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 VCC GND I/O4 I/O5 I/O6 I/O7 WE A15 A14 A13 A12 NC 1 2 3 4 5 6 7 8 |
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Alliance Semiconductor Corporation |
(AS7C33128NTF32B / AS7C33128NTF36B) 3.3V 128K x 32/36 Flowthrough Synchronous SRAM • Organization: 131,072 words × 32 or 36 bits • NTD™architecture for efficient bus operation • Fast clock to data access: 7.5/8.0/10.0 ns • Fast OE access time: 3.5/4.0 ns • Fully synchronous operation • Flow-through mode • Asynchronous output enable |
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Alliance Semiconductor Corporation |
3.3V 128Kx18 Pipelined SRAM • Organization: 131,072 words × 18 bits • NTD™ architecture for efficient bus operation • Fast clock speeds to 200 MHz • Fast clock to data access: 3.0/3.5/4.0 ns • Fast OE access time: 3.0/3.5/4.0 ns • Fully synchronous operation • Asynchronous outp |
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Alliance Semiconductor Corporation |
(AS7C33128PFD32A / AS7C33128PFD36A) 3.3V 128K X 32/36 pipeline burst synchronous SRAM • Organization: 131,072 words × 32 or 36 bits • Fast clock speeds to 166 MHz in LVTTL/LVCMOS • Fast clock to data access: 3.5/3.8/4.0/5.0 ns • Fast OE access time: 3.5/3.8/4.0/5.0 ns • Fully synchronous register-to-register operation • Single registe |
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Alliance Semiconductor Corporation |
3.3V 2M x 18 Pipelined SRAM • Organization: 2,097,152 words × 18 bits • NTD™ architecture for efficient bus operation • Fast clock speeds to 200 MHz • Fast clock to data access: 3.2/3.5/3.8 ns • Fast OE access time: 3.2/3.5/3.8 ns • Fully synchronous operation • Common data inp |
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Alliance Semiconductor Corporation |
5V 128K x 8 CMOS SRAM • Industrial and commercial temperatures • Organization: 131,072 x 8 bits • High speed - 10/12/15/20 ns address access time - 5/6/7/8 ns output enable access time • Low power consumption: ACTIVE - 605mW / max @ 10 ns • Low power consumption: STANDBY |
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Alliance Semiconductor |
3.3 V 256 K x 16 CMOS SRAM • Pin compatible with AS7C34098 • Industrial and commercial temperature • Organization: 262,144 words × 16 bits • Center power and ground pins • High speed • Low power consumption: ACTIVE • Low power consumption: STANDBY • Individual byte read/write |
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Alliance Semiconductor |
5V/3.3V 256K x 16 CMOS SRAM • AS7C4098 (5V version) • AS7C34098 (3.3V version) • Industrial and commercial temperature • Organization: 262,144 words × 16 bits • Center power and ground pins • High speed - 10/12/15/20 ns address access time - 5/6/7/8 ns output enable access time |
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Alliance Semiconductor |
3.3V 256K X 16/18 SRAM • Organization: 262,144 words × 16 or 18 bits • NTD™1 architecture for efficient bus operation • Fast clock speeds to 166 MHz in LVTTL/LVCMOS • Fast clock to data access: 3.5/4.0/5.0 ns • Fast OE access time: 3.5/4.0/5.0 ns • Fully synchronous operat |
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Alliance Semiconductor |
3.3V 128K X 32/36 SRAM • Organization: 131,072 words × 32 or 36 bits NTD™1 architecture for efficient bus operation • Fast clock speeds to 166 MHz in LVTTL/LVCMOS • Fast clock to data access: 3.5/4.0/5.0 ns • Fast OE access time: 3.5/4.0/5.0 ns • Fully synchronous operatio |
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Alliance Semiconductor |
5V/3.3V 128K x 8 CMOS SRAM • AS7C1025 (5V version) • AS7C31025 (3.3V version) • Industrial and commercial temperatures • Organization: 131,072 words × 8 bits • High speed - 12/15/20 ns address access time - 6,7,8 ns output enable access time • Low power consumption: ACTIVE - 7 |
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Alliance Semiconductor |
5V/3.3V 32K x 8 CMOS SRAM • AS7C256 (5V version) • AS7C3256 (3.3V version) • Industrial and commercial temperature • Organization: 262,144 words × 16 bits • High speed - 12/15/20 ns address access time - 5/6/7/9 ns output enable access time • Very low power consumption: ACTIV |
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Alliance Semiconductor |
3.3V 32K x 8 CMOS SRAM • Pin compatible with AS7C3256 • Industrial and commercial temperature options • Organization: 32,768 words × 8 bits • High speed - 10/12/15/20 ns address access time - 5, 6, 7, 8 ns output enable access time • Very low power consumption: ACTIVE - 18 |
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Alliance Semiconductor |
32K x 8 CMOS SRAM • Organization: 32,768 words × 8 bits • High speed – 10/12/15/20/25/35 ns address access time – 3/3/4/5/6/8 ns output enable access time • Low power consumption – Active: 660 mW max (10 ns cycle) – Standby: 11 mW max, CMOS I/O 2.75 mW max, CMOS I/O, |
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Alliance Semiconductor Corporation |
(AS7C33128FT32B / AS7C33128FT36B) 3.3V 128K x 32/36 Flow Through Synchronous SRAM • • • • • • • Organization: 131,072 words × 32 or 36 bits Fast clock to data access: 6.5/7.5/8.0/10.0 ns Fast OE access time: 3.5/4.0 ns Fully synchronous flow through operation Asynchronous output enable control Available in 100-pin TQFP package Ind |
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Alliance Semiconductor Corporation |
3.3V 128K x 18 Flowthrough Synchronous SRAM • • • • • • • • Organization: 131,072 words × 18 bits NTD™ architecture for efficient bus operation Fast clock to data access: 7.5/8.0/10.0 ns Fast OE access time: 3.5/4.0 ns Fully synchronous operation Flow-through mode Asynchronous output enable co |
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Alliance Semiconductor Corporation |
(AS7C33128NTF32B / AS7C33128NTF36B) 3.3V 128K x 32/36 Flowthrough Synchronous SRAM • Organization: 131,072 words × 32 or 36 bits • NTD™architecture for efficient bus operation • Fast clock to data access: 7.5/8.0/10.0 ns • Fast OE access time: 3.5/4.0 ns • Fully synchronous operation • Flow-through mode • Asynchronous output enable |
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Alliance Semiconductor Corporation |
3.3V 128K x 18 pipeline burst synchronous SRAM • Organization: 131,072 words × 18 bits • Fast clock speeds to 200 MHz • Fast clock to data access: 3.0/3.5/4.0 ns • Fast OE access time: 3.0/3.5/4.0 ns • Fully synchronous register-to-register operation • Double-cycle deselect • Asynchronous output |
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Alliance Semiconductor Corporation |
(AS7C33128PFD32B / AS7C33128PFD36B) 3.3V 128K X 32/36 pipeline burst synchronous SRAM • Organization: 131,072 words × 32 or 36 bits • Fast clock speeds to 200 MHz • Fast clock to data access: 3.0/3.5/4.0 ns • Fast OE access time: 3.0/3.5/4.0 ns • Fully synchronous register-to-register operation • Double-cycle deselect • Asynchronous o |
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Alliance Semiconductor Corporation |
(AS7C33128PFS32A / AS7C33128PFS36A) 3.3V 128K X 32/36 pipeline burst synchronous SRAM • Organization: 131,072 words × 32 or 36 bits • Fast clock speeds to 200 MHz in LVTTL/LVCMOS • Fast clock to data access: 3.0/3.1/3.5/4.0/5.0 ns • Fast OE access time: 3.0/3.1/3.5/4.0/5.0 ns • Fully synchronous register-to-register operation • Single |
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Desde 2024. D4U Semiconductor.
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