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Adjustable precision shunt regulators and benefits • Programmable output voltage up to 36 V • Three different reference voltage tolerances: • • Standard grade: 2 % • A-Grade: 1 % • B-Grade: 0.5 % • Typical temperature drift: 9 mV (in a range of 0 °C up to 70 °C) • Low output noise • Typi |
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Adjustable precision shunt regulators and benefits • Programmable output voltage up to 36 V • Three different reference voltage tolerances: • • Standard grade: 2 % • A-Grade: 1 % • B-Grade: 0.5 % • Typical temperature drift: 9 mV (in a range of 0 °C up to 70 °C) • Low output noise • Typi |
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Octal D-type transparent latch latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches |
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Schottky barrier diode and benefits Low forward voltage Low capacitance AEC-Q101 qualified 1.3 Applications Ultra high-speed switching Line termination Voltage clamping Reverse polarity protection 1.4 Quick reference data Table 1. Quick reference data Tam |
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Quad 2-input AND gate and benefits • Wide supply voltage range from 2.0 V to 6.0 V • CMOS low power dissipation • High noise immunity • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B • Input levels: • For 74HC08: CMOS level • For 74HCT08: TTL level • Com |
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dual N-channel MOSFET and benefits Logic-level compatible Very fast switching Trench MOSFET technology ESD protection up to 2 kV AEC-Q101 qualified 1.3 Applications Relay driver High-speed line driver Low-side loadswitch Switching circuits 1.4 Quick re |
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Coin cell battery life booster and benefits • Programmable constant battery load current: 2 mA to 16 mA • Protection against battery voltage dips (Brown-out) • Pulse output current: > 150 mA • Low ripple regulated programmable output voltage, VDH: 1.8 V to 3.6 V • Ultra-low standb |
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ESD protection and benefits • Allows switching between PCMFxUSB3B/C common mode filters with ESD protection and PESDxUSB3B/C ESD protection in the same footprint • TrEOS protection process for very high system-level ESD robustness: superior protection of sensitive |
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N-channel MOSFET and benefits Logic-level compatible Very fast switching Trench MOSFET technology ESD protection up to 2 kV AEC-Q101 qualified 1.3 Applications Relay driver High-speed line driver Low-side loadswitch Switching circuits 1.4 Quick re |
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Dual retriggerable monostable multivibrator and benefits • Wide supply voltage range from 2.0 V to 6.0 V • CMOS low power dissipation • High noise immunity • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B • Complies with JEDEC standards: • JESD8C (2.7 V to 3.6 V) • JESD7A (2. |
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Dual D-type flip-flop and benefits • Wide supply voltage range from 2.0 to 6.0 V • CMOS low power dissipation • High noise immunity • Input levels: • For 74HC74: CMOS level • For 74HCT74: TTL level • Symmetrical output impedance • High noise immunity • Balanced propagatio |
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shift register two serial data inputs (DSA and DSB), eight parallel data outputs (Q0 to Q7). Data is entered serially through DSA or DSB and either input can be used as an active HIGH enable for data entry through the other input. Data is shifted on the LOW-to-HIGH |
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3-to-8 line decoder/demultiplexer three enable inputs (E1 and E2 and E3). Every output will be LOW unless E1 and E2 are LOW and E3 is HIGH. This multiple enable function allows easy parallel expansion to a 1-of-32 (5 to 32 lines) decoder with just four '238 ICs and one inverter. The |
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Hex inverting Schmitt trigger reduced input threshold levels to allow interfacing to TTL logic levels. Inputs also include clamp diodes, this enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. Schmitt trigger inputs transform slowly ch |
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14-stage binary ripple counter and benefits • Wide supply voltage range from 2.0 V to 6.0 V • CMOS low power dissipation • High noise immunity • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B • Complies with JEDEC standards: • JESD8C (2.7 V to 3.6 V) • JESD7A (2. |
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16-bit buffer/line driver and benefits • Wide supply voltage range from 1.2 V to 3.6 V • Complies with JEDEC standards: – JESD8-7 (1.2 V to 1.95 V) – JESD8-5 (1.8 V to 2.7 V) – JESD8-1A (2.7 V to 3.6 V) • CMOS low power consumption • Input/output tolerant up to 3.6 V • Dynam |
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Octal bus transceiver an output enable (OE) and send/receive (DIR) for direction control. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translato |
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Schottky barrier diodes and benefits • Low forward voltage • Low capacitance 3. Applications • Ultra high-speed switching • Line termination • Voltage clamping • Reverse polarity protection 4. Quick reference data Table 1. Quick reference data Symbol Parameter VR rev |
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Dual 4-channel analog multiplexer/demultiplexer four independent inputs/outputs (nY0, nY1, nY2 and nY3) and a common input/output (nZ). A digital enable input (E) and two digital select inputs (S0 and S1) are common to both switches. When E is HIGH, the switches are turned off. Inputs include clam |
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serial or parallel-out shift register a serial input (DS) and a serial output (Q7S) to enable cascading and an asynchronous reset MR input. A LOW on MR will reset the shift register. Data is shifted on the LOW-to-HIGH transitions of the SHCP input. The data in the shift register is trans |
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Desde 2024. D4U Semiconductor.
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