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Octal D-type transparent latch latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches |
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Quad 2-input AND gate and benefits • Wide supply voltage range from 2.0 V to 6.0 V • CMOS low power dissipation • High noise immunity • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B • Input levels: • For 74HC08: CMOS level • For 74HCT08: TTL level • Com |
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shift register two serial data inputs (DSA and DSB), eight parallel data outputs (Q0 to Q7). Data is entered serially through DSA or DSB and either input can be used as an active HIGH enable for data entry through the other input. Data is shifted on the LOW-to-HIGH |
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3-to-8 line decoder/demultiplexer three enable inputs (E1 and E2 and E3). Every output will be LOW unless E1 and E2 are LOW and E3 is HIGH. This multiple enable function allows easy parallel expansion to a 1-of-32 (5 to 32 lines) decoder with just four '238 ICs and one inverter. The |
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Hex inverting Schmitt trigger reduced input threshold levels to allow interfacing to TTL logic levels. Inputs also include clamp diodes, this enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. Schmitt trigger inputs transform slowly ch |
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Dual retriggerable monostable multivibrator and benefits • Wide supply voltage range from 2.0 V to 6.0 V • CMOS low power dissipation • High noise immunity • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B • Complies with JEDEC standards: • JESD8C (2.7 V to 3.6 V) • JESD7A (2. |
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Dual D-type flip-flop and benefits • Wide supply voltage range from 2.0 to 6.0 V • CMOS low power dissipation • High noise immunity • Input levels: • For 74HC74: CMOS level • For 74HCT74: TTL level • Symmetrical output impedance • High noise immunity • Balanced propagatio |
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Quad 2-input EXCLUSIVE-OR gate and benefits • Wide supply voltage range from 2.0 V to 6.0 V • CMOS low power dissipation • High noise immunity • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B • Complies with JEDEC standards: • JESD8C (2.7 V to 3.6 V) • JESD7A (2. |
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Quad D-type flip-flop clock (CP), master reset (MR), two input enable (E1, E2) and two output enable (OE1, OE2) inputs. When the input enables are LOW, the outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on |
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Dual 4-channel analog multiplexer/demultiplexer four independent inputs/outputs (nY0, nY1, nY2 and nY3) and a common input/output (nZ). A digital enable input (E) and two digital select inputs (S0 and S1) are common to both switches. When E is HIGH, the switches are turned off. Inputs include clam |
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Dual buffer/line driver and benefits • Wide supply voltage range from 2.0 V to 6.0 V • Input levels: • For 74HC2G125: CMOS level • For 74HCT2G125: TTL level • Symmetrical output impedance • High noise immunity • Low power dissipation • Balanced propagation delays • ESD prot |
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Quad D-type flip-flop and benefits • Input levels: • For 74HC175: CMOS level • For 74HCT175: TTL level • Four edge-triggered D-type flip-flops • Asynchronous master reset • Complies with JEDEC standard no. 7A • ESD protection: • HBM JESD22-A114F exceeds 2000 V • MM JESD22 |
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Octal D-type flip-flop clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A LOW on MR forces the outputs LOW independently |
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14-stage binary ripple counter and benefits • Wide supply voltage range from 2.0 V to 6.0 V • CMOS low power dissipation • High noise immunity • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B • Complies with JEDEC standards: • JESD8C (2.7 V to 3.6 V) • JESD7A (2. |
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3-to-8 line decoder/demultiplexer three enable inputs (E1, E2 and E3). Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH. This multiple enable function allows easy parallel expansion to a 1-of-32 (5 to 32 lines) decoder with just four '138 ICs and one inverter. The '1 |
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Dual JK flip-flop reduced input threshold levels to allow interfacing to TTL logic levels. Inputs also include clamp diodes, this enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. Schmitt-trigger action in the clock input |
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Quad 2-input OR gate and benefits • Wide supply voltage range from 2.0 to 6.0 V • CMOS low power dissipation • High noise immunity • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B • Complies with JEDEC standards: • JESD8C (2.7 V to 3.6 V) • JESD7A (2.0 |
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Octal bus transceiver an output enable (OE) and send/receive (DIR) for direction control. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages |
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Quad 2-input NAND gate and benefits • Wide supply voltage range from 2.0 to 6.0 V • CMOS low power dissipation • High noise immunity • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B • Input levels: • For 74HC00: CMOS level • For 74HCT00: TTL level • Compl |
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Dual JK flip-flop individual J and K inputs, clock (nCP) set (nSD) and reset (nRD) inputs. It also has complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. The J and K inputs control the st |
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Desde 2024. D4U Semiconductor.
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