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16-bit buffer/line driver and benefits • Wide supply voltage range from 1.2 V to 3.6 V • Complies with JEDEC standards: – JESD8-7 (1.2 V to 1.95 V) – JESD8-5 (1.8 V to 2.7 V) – JESD8-1A (2.7 V to 3.6 V) • CMOS low power consumption • Input/output tolerant up to 3.6 V • Dynam |
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16-bit bus transceiver and transparant D-type latch direction (1DIR, 2DIR), latch enable (1LOE, 2LOE), transceiver output enable (1TOE, 2TOE) and latch enable (1LE, 2LE) control inputs; four 8-bit transceiver ports (1An, 2An & 1Bn, 2Bn); two 8-bit D-type latch output ports (1Qn, 2Qn) and an 8-bit buff |
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16-bit dual supply translating transceiver and benefits • Wide supply voltage range: • 3 V port (VCC(A)): 1.5 V to 3.6 V • 5 V port (VCC(B)): 1.5 V to 5.5 V • CMOS low power consumption • Overvoltage tolerant inputs to 5.5 V • Direct interface with TTL levels • IOFF circuitry provides partial |
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Octal buffer/line driver two output enables (1OE and 2OE), each controlling four of the 3-state outputs. A HIGH on nOE causes the outputs to assume a high-impedance OFF-state. Inputs are overvoltage tolerant. This feature allows the use of these devices as translators in mix |
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14-stage divider/oscillator and benefits • Wide supply voltage range from 2.0 V to 5.5 V • Overvoltage tolerant inputs to 5.5 V • High noise immunity • CMOS low power dissipation • ESD protection: • HBM JESD22-A114F: exceeds 2000 V • CDM JESD22-C101E: exceeds 1000 V • Latch-up |
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20-bit bus interface D-type flip-flop two clocks (1CP and 2CP) and two output enables (1OE and 2OE), each controlling 10-bits. The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (nCP) transition. A HIG |
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Low-power 2-input NAND gate and benefits • Wide supply voltage range from 0.7 V to 2.75 V • Low input capacitance; CI = 0.5 pF (typical) • Low output capacitance; CO = 1.0 pF (typical) • Low dynamic power consumption; CPD = 2.5 pF at VCC = 1.2 V (typical) • Low static power con |
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Low-power 2-input NOR gate and benefits • Wide supply voltage range from 0.7 V to 2.75 V • Low input capacitance; CI = 0.5 pF (typical) • Low output capacitance; CO = 1.0 pF (typical) • Low dynamic power consumption; CPD = 2.6 pF at VCC = 1.2 V (typical) • Low static power con |
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nexperia |
Low-power D-type flip-flop and benefits • Wide supply voltage range from 0.8 V to 3.6 V • CMOS low power dissipation • High noise immunity • Complies with JEDEC standards: • JESD8-12 (0.8 V to 1.3 V) • JESD8-11 (0.9 V to 1.65 V) • JESD8-7 (1.65 V to 1.95 V) • JESD8-5 (2.3 V to |
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18-bit buffer/driver and benefits • Wide supply voltage range of 1.2V to 3.6V • CMOS low power consumption • MultiByte flow-through standard pin-out architecture • Low inductance multiple VCC and GND pins for minimum noise and ground bounce • Direct interface with TTL l |
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Low-power X-tal driver and benefits • Wide supply voltage range from 0.8 V to 3.6 V • CMOS low power dissipation • High noise immunity • Overvoltage tolerant inputs to 3.6 V • Low noise overshoot and undershoot < 10 % of VCC • IOFF circuitry provides partial Power-down mod |
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15-stage divider/oscillator and benefits • Wide supply voltage range from 2.0 V to 5.5 V • Overvoltage tolerant inputs to 5.5 V • High noise immunity • CMOS low power dissipation • ESD protection: • HBM: ANSI/ESDA/Jedec JS-001 exceeds 2000 V • CDM: ANSI/ESDA/Jedec JS-002 exceed |
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nexperia |
16-bit edge-triggered D-type flip-flop two clocks (1CP and 2CP) and two output enables (1OE and 2OE), each controlling 8-bits. The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (nCP) transition. A HIGH |
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nexperia |
16-bit edge-triggered D-type flip-flop two clocks (1CP and 2CP) and two output enables (1OE and 2OE), each controlling 8-bits. The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (nCP) transition. A HIGH |
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Octal bus transceiver an output enable (OE) and send/receive (DIR) for direction control. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Inputs are overvoltage tolerant. This feature allows the use of these devices as translators in mixed voltage en |
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14-stage divider/oscillator and benefits • Automotive product qualification in accordance with AEC-Q100 (Grade 1) • Specified from -40 °C to +85 °C and from -40 °C to +125 °C • Wide supply voltage range from 2.0 V to 5.5 V • Overvoltage tolerant inputs to 5.5 V • High noise imm |
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18-bit bus-interface D-type flip-flop clock (nCP), clock enable (nCE), master reset (nMR) and output enable (nOE, inputs each controlling 9-bits. When nCE is LOW, the flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-t |
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nexperia |
10-stage divider/oscillator and benefits • Wide supply voltage range from 2.0 V to 5.5 V • Overvoltage tolerant inputs to 5.5 V • High noise immunity • CMOS low power dissipation • Latch-up performance exceeds 100 mA per JESD 78 Class II • ESD protection: • HBM JESD22-A114F: ex |
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8-bit serial-in/parallel-out shift register two serial data inputs (DSA and DSB), eight parallel data outputs (Q0 to Q7). Data is entered serially through DSA or DSB and either input can be used as an active HIGH enable for data entry through the other input. Data is shifted on the LOW-to-HIGH |
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8-bit serial-in/serial-out or parallel-out shift register a serial input (DS) and a serial output (Q7S) to enable cascading and an asynchronous reset MR input. A LOW on MR will reset the shift register. Data is shifted on the LOW-to-HIGH transitions of the SHCP input. The data in the shift register is trans |
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Desde 2024. D4U Semiconductor.
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