| No. | parte # | Fabricante | Descripción | Hoja de Datos |
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Texas Instruments |
48-Bit LVDS 1 •2 Up to 5.38 Gbits/sec Bandwidth • 33 MHz to 112 MHz Input Clock Support • LVDS SER/DES Reduces Cable and Connector Size • Pre-emphasis Reduces Cable Loading Effects • DC Balance Data Transmission Provided by Transmitter Reduces ISI Distortion • C |
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Texas Instruments |
48-Bit LVDS 1 •2 Up to 5.38 Gbits/sec Bandwidth • 33 MHz to 112 MHz Input Clock Support • LVDS SER/DES Reduces Cable and Connector Size • Pre-emphasis Reduces Cable Loading Effects • DC Balance Data Transmission Provided by Transmitter Reduces ISI Distortion • C |
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Texas Instruments |
HIGH-SPEED DIFFERENTIAL RECEIVERS that implement the electrical characteristics of low-voltage differential signaling (LVDS). LVDS is defined in the TIA/EIA-644 standard. This improved performance represents the second generation of receiver products for this standard providing a bet |
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Texas Instruments |
Dual Pixel LVDS Display Interface 1 •2 Complies with OpenLDI Specification for Digital Display Interfaces • 32.5 to 112/170MHz Clock Support for DS90C387, 40 to 112MHz Clock Support for DS90CF388 • Supports SVGA through QXGA Panel Resolutions • Drives Long, Low Cost Cables • Up to 5. |
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Texas Instruments |
Dual 4.16Gbps FPD-Link3 Deserializer Hub • AEC-Q100 qualified for automotive applications – Device temperature grade 2: –40℃ to +105℃ ambient operating temperature range • Dual deserializer hub aggregates one or two active sensors over FPD-Link III interface • Power-Over-Coax (PoC) compatib |
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Texas Instruments |
48-Bit Channel Link Serializer •1 Up to 6.384-Gbps Throughput • 66-MHz to 133-MHz Input Clock Support • Reduces Cable and Connector Size and Cost • Pre-Emphasis Reduces Cable Loading Effects • DC Balance Reduces ISI Distortion • 24-Bit Double Edge Inputs • 3-V Tolerant LVCMOS/LVTT |
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Texas Instruments |
2K FPD-Link3 to OpenLDI Deserializer •1 Qualified for Automotive Applications • AEC-Q100 Qualified With the Following Results: – Device Temperature Grade 2: –40°C to +105°C Ambient Operating Temperature • Supports Pixel Clock Frequency up to 192 MHz for up to 2K (2048x1080) Resolutions |
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Texas Instruments |
24-bit Color FPD-Link2 Serializer/Deserializer •1 5- to 65-MHz PCLK support (140 Mbps to 1.82 Gbps) • AC-Coupled STP interconnect cable up to 10 meters • Integrated terminations on serializer and deserializer • At speed link BIST mode and reporting pin • Optional I2C-compatible serial control bus |
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Texas Instruments |
High-Speed Differential Line Drivers • Meet or Exceed the Requirements of ANSI TIA/ EIA-644 Standard • Low-Voltage Differential Signaling With Typical Output Voltage of 350 mV and 100-Ω Load • Typical Output Voltage Rise and Fall Times of 500 ps (400 Mbps) • Typical Propagation Delay Ti |
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ETCTI |
DS92UT16 UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers (Rev. E) |
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Texas Instruments |
+3.3V Programmable LVDS Transmitter 1 •23 No Special Start-up Sequence Required Between Clock/Data and /PD Pins. Input Signal (Clock and Data) Can be Applied Either Before or After the Device is Powered. • Support Spread Spectrum Clocking Up to 100KHz Frequency Modulation & Deviations |
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Texas Instruments |
+3.3V LVDS Receiver 1 •2 Automotive Grade Device, AEC-Q100 Grade 3 Qualified • Operating Temperature Range: –40°C to +85°C • 20 to 65 MHz Shift Clock Support • 50% Duty Cycle on Receiver Output Clock • Best –in –Class Set & Hold Times on RxOUTPUTs • Rx Power Consumption < |
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Texas Instruments |
+3.3V Rising Edge Data Strobe LVDS 1 • 20 to 85 MHz Shift Clock Support • 50% Duty Cycle on Receiver Output Clock • 2.5 / 0 ns Set & Hold Times on TxINPUTs • Low Power Consumption • ±1V Common-Mode Range (around +1.2V) • Narrow Bus Reduces Cable Size and Cost • Up to 2.38 Gbps Through |
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Texas Instruments |
48-Bit LVDS |
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Texas Instruments |
5-MHz to 85-MHz 24-Bit Color FPD-Link3 Serializer •1 Integrated HDCP Cipher Engine with On-Chip Key Storage • Bidirectional Control Channel Interface with I2C Compatible Serial Control Bus • Low EMI FPD-Link Video Input • Supports High Definition (720p) Digital Video Format • 5-MHz to 85-MHz PCLK Su |
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Texas Instruments |
100 MHz M-LVDS Line Driver/Receiver Pair 1 •2 DC to 100+ MHz / 200+ Mbps Low Power, Low EMI Operation • Optimal for ATCA, uTCA Clock Distribution Networks • Meets or Exceeds TIA/EIA-899 M-LVDS Standard • Wide Input Common Mode Voltage for Increased Noise Immunity • DS91D180 has Type 1 Recei |
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Texas Instruments |
Link-II Serializer/Deserializer 1 •2 Wide Operating Range Embedded Clock SER/DES – Up to 32-bit Parallel LVCMOS Data – 20 to 85 MHz Parallel Clock – Up to 2.72 Gbps Application Data Paylod • Selectable Serial LVDS Bus Width – Dual Lane Mode (20 to 50 MHz) – Quad Lane Mode (40 to 85 |
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Texas Instruments |
High-Speed Differential Line Receivers •1 Meet or Exceed the Requirements of ANSI TIA/EIA-644 Standard • Operate With a Single 3.3-V Supply • Designed for Signaling Rates of up to 150 Mbps (See ) • Differential Input Thresholds ±100 mV Max • Typical Propagation Delay Time of 2.1 ns • Powe |
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Texas Instruments |
HIGH-SPEED DIFFERENTIAL LINE RECEIVERS 6 2A 5 2B the power, increase the switching speeds, and allow operation with a 3.3-V supply rail. Any of the four differential receivers provides a valid logical output state with a ±100 mV allow operation with a differential input voltage within |
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Texas Instruments |
TRANSMITTER •1 AEC-Q100 Qualified with: – Temperature Grade 3: –40°C to 85°C – HBM ESD Classification 3 – CDM ESD Classification C6 • LVDS Display Series Interfaces Directly to LCD Display Panels With Integrated LVDS • Package: 14-mm x 6.1-mm TSSOP • 1.8-V Up to |
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Desde 2024. D4U Semiconductor.
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