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Texas Instruments |
SCAN TEST DEVICE -mil Center-to-Center Spacings SN54ABT18502 . . . HV PACKAGE (TOP VIEW) 1A2 1A1 1OEAB GND 1LEAB 1CLKAB TDO VCC NC TMS 1CLKBA 1LEBA 1OEBA GND 1B1 1B2 1B3 1A3 1A4 1A5 GND 1A6 1A7 1A8 1A9 NC VCC 2A1 2A2 2A3 GND 2A4 2A5 2A6 9 8 7 6 5 4 3 2 1 68 67 66 |
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Texas Instruments |
16-BIT REGISTERED TRANSCEIVERS t control in either direction of data flow. The A-to-B enable (CEAB) input must be low to enter data from A or to output data to B. If both CEAB and CLKAB are low, then B port will have the level of A port prior to the most recent low-to-high transit |
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Texas Instruments |
OCTAL BUS TRANSCEIVERS T623A and SN74ABT623 bus transceivers are designed for asynchronous communication between data buses. The control-function implementation allows for maximum flexibility in timing. The SN54ABT623A and SN74ABT623 provide true data at their outputs. A3 |
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Texas Instruments |
16-BIT BUFFERS/DRIVERS SN54ABT16240A, SN74ABT16240A 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCBS095G – DECEMBER 1991 – REVISED OCTOBER 1998 SN54ABT16240A . . . WD PACKAGE SN74ABT16240A . . . DGG, DGV, OR DL PACKAGE (TOP VIEW) 1OE 1 1Y1 2 1Y2 3 GND 4 1Y3 5 1Y4 6 VCC 7 |
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Texas Instruments |
Octal D-Type Flip-Flop 260C-UNLIM N / A for Pkg Type Level-1-260C-UNLIM Level-1-260C-UNLIM -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 Device Marking (4/5) CD54AC574F3A CD54ACT574F3A CD74AC574E AC574M AC574M CD74ACT574E ACT574M ACT574M (1) The mark |
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Texas Instruments |
16-Bit Buffer/Drivers or one 16-bit buffer. These devices provide true outputs and complementary output-enable (OE and OE) inputs. 54ACT16241 . . . WD PACKAGE 74ACT16241 . . . DL PACKAGE (TOP VIEW) 1OE 1Y1 1Y2 GND 1Y3 1Y4 VCC 2Y1 2Y2 GND 2Y3 2Y4 3Y1 3Y2 GND 3Y3 3Y4 VCC |
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Texas Instruments |
Octal Buffers/Drivers •1 Operating Range 2-V to 5.5-V VCC • Latch-Up Performance Exceeds 250 mA Per JESD 17 • On Products Compliant to MIL-PRF-38535, All Parameters Are Tested Unless Otherwise Noted. On All Other Products, Production Processing Does Not Necessarily Includ |
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Texas Instruments |
Dual 1-of-4 Data Selectors/Multiplexers gates. Separate strobe inputs (G) are provided for each of the two four-line sections. 3 2 1 20 19 1C1 4 18 2C1 1C0 5 17 2C2 NC 6 16 NC A7 15 2C3 B8 14 2G 9 10 11 12 13 1Y GND NC 2Y 1G The 3-state outputs can interface with and drive d |
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Texas Instruments |
16-Bit Buffers/Drivers •1 Members of the Texas Instruments Widebus™ Family • EPIC™ (Enhanced-Performance Implanted CMOS) Process • Operating Range 2-V to 5.5-V VCC • Distributed VCC and GND Pins Minimize High-Speed Switching Noise • Flow-Through Architecture Optimizes PCB |
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Texas Instruments |
HEX INVERTER 1 • Operating Range 2-V to 5.5-V • Latch-Up Performance Exceeds 250 mA Per JESD 17 • ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) SN54AHC04 . . . JORWP ACKAGE |
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Texas Instruments |
16-BIT D-TYPE TRANSPARENT LATCHES nal bus drivers, and working registers. These devices can be used as two 8-bit latches or one 16-bit latch. The Q outputs of the latches follow the data (D) inputs if enable C is taken high. When C is taken low, the Q outputs are latched at the level |
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Texas Instruments |
QUADRUPLE BUS BUFFER GATES independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low. When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure t |
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Texas Instruments |
Octal D-Type Flip-Flop 260C-UNLIM N / A for Pkg Type Level-1-260C-UNLIM Level-1-260C-UNLIM -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 Device Marking (4/5) CD54AC574F3A CD54ACT574F3A CD74AC574E AC574M AC574M CD74ACT574E ACT574M ACT574M (1) The mark |
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Texas Instruments |
Hex Schmitt-Trigger Inverters •1 ESD Protection Exceeds JESD 22: – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) • Operating Range: 2 V to 5.5 V • ±8-mA Output Drive at 5 V • Schmitt-Trigger Inputs Enable Input Noise Resistan |
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Texas Instruments |
Quadruple 2-Input Positive-AND Gate • 2V to 5.5V operating range • Latch-up performance exceeds 250mA per JESD 17 • ESD protection exceeds JESD 22 2 Applications • Servers • Network Switches • PCs and Notebooks • Electronic Points of Sale 3 Description The SNx4AHC08 devices are quadr |
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Texas Instruments |
16-BIT TRANSPARENT D-TYPE LATCHES two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs. 54AC16373 . . . WD PACKAGE 74AC16373 . . |
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Texas Instruments |
16-Bit Bus Transceivers from the B bus to the A bus, depending on the logic level at the output-enable (OEAB or OEBA) inputs. The output-enable inputs can be used to disable the device so that the buses are effectively isolated. 54ACT16620 . . . WD PACKAGE 74ACT16620 . . |
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Texas Instruments |
QUADRUPLE 2-INPUT POSITIVE-NAND BUFFERS E (TOP VIEW) 1A 1B 1Y 2A 2B 2Y GND 1 2 3 4 5 6 7 14 VCC 13 4B 12 4A 11 4Y 10 3B 9 3A 8 3Y SN54ALS38B . . . FK PACKAGE (TOP VIEW) 1B 1A NC VCC 4B 3 2 1 20 19 1Y 4 18 4A NC 5 17 NC 2A 6 16 4Y NC 7 15 NC 2B 8 14 3B 9 10 11 12 13 2Y GND |
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Texas Instruments |
Hex Inverters 2A 5 3A 9 4A 11 5A 13 6A 2 1Y 4 2Y 6 3Y 8 4Y 10 5Y 12 6Y † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, J, and N packages. NC − No internal connection logic diagram |
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Texas Instruments |
Quadruple 2-Input Positive-NAND Gates 10 3B 12 4A 13 4B 3 1Y 6 2Y 8 3Y 11 4Y † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, J, and N packages. 3 2 1 20 19 1Y 4 18 4A NC 5 17 NC 2A 6 16 4Y NC 7 15 NC |
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Desde 2024. D4U Semiconductor.
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