| No. | parte # | Fabricante | Descripción | Hoja de Datos |
|---|---|---|---|---|
|
|
|
ams |
Battery Cell Monitor and Balancer IC cell voltage diagnosis with externally adjustable upper and lower cell voltage limits, fast cell voltage capture on request through 12-bit SAR ADC, passive cell balancing by simultaneous comparison of actual cell voltages with a reference cell voltag |
|
|
|
|
Alliance Semiconductor |
3.3V Synchronous SRAMs 128K x 36, 256K x 18 memory configurations Supports high system speed: Commercial: – 150MHz 3.8ns clock access time LBO input selects interleaved or linear burst mode Self-timed write cycle with global write control ( GW l ( ), byte write enable (BW |
|
|
|
|
Alliance Semiconductor |
3.3V Synchronous SRAMs ◆ ◆ AS8C403625 AS8C401825 Description TheAS8C403625/1825 are high-speed SRAMs organized as 128K x 36/256K x 18. The AS8C403625/1825 SRAMs contain write, data, address and control registers. There are no registers in the data output path (flow- |
|
|
|
|
Alliance Semiconductor |
2.5V Synchronous SRAMs |
|
|
|
|
ams |
TTP-C2NF Communication Controller Dual-channel controller for redundant data transfers Dedicated controller supporting TTP (time-triggered protocol class C standardized in SAE 6003) Suited for dependable distributed real-time systems with guaranteed response time Asynchronous |
|
|
|
|
Alliance Semiconductor |
3.3V Synchronous SRAMs 128K x 36, 256K x 18 memory configurations Supports high system speed: Commercial: – 150MHz 3.8ns clock access time LBO input selects interleaved or linear burst mode Self-timed write cycle with global write control ( GW l ( ), byte write enable (BW |
|
|
|
|
Alliance Semiconductor |
3.3V Synchronous SRAMS 3.3V I/O, burst counter, and Pipelined Outputs Commercial Temperature Ranges AS8C403601-QC166N AS8C401801-QC166N 403601/401801 403601/401801 403601/401801 NOVEMBER 1 AS8C403601, AS8C401801,128K x 36, 256K x 18, 3.3V Synchronous SRAMS with ZBT™ F |
|
|
|
|
Alliance Semiconductor |
3.3V Synchronous SRAMs 256K x 36, 512K x 18 memory configurations Supports high system speed: – 150MHz 3.8ns clock access time ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ LBO input selects interleaved or linear burst mode Self-timed write cycle with global write control (GW), byte write enable (BWE |
|
|
|
|
ams |
LIN Transceiver Operating voltage 4.3V to 18V, max. 42V for 500 ms Two linear low-drop voltage regulators: VCC = 3.3V with 50mA drive capability Typical 50µA quiescent current in standby mode Typical 35µA quiescent current in sleep mode Precision voltage a |
|
|
|
|
ams |
High-efficient Power Management Device The AS8650B is a companion IC which combines power management functions and a fully conforming high-speed CAN Transceiver in one high performance analog device for automotive applications. The AS8650B is powered by the battery, provides 4 output vol |
|
|
|
|
ams |
LIN Transceiver ep-SOIC8 package -40ºC to +125ºC ambient operating temperature Operating voltage 6V to 18V Linear, low-drop voltage regulator: VCC = 5V ±5% or 3.3V ±5% as a factory programming option 50mA load current Operating modes: Normal and Standb |
|
|
|
|
ams |
Data Acquisition System A precision voltage attenuator with power down facility LIN 2.1 transceiver Power-On Reset with programmable reset timeout and brownout detection through factory setting A window Watchdog function in the normal mode and a timeout Watchdog in |
|
|
|
|
ams |
Capacitive Sensor .............................. 3 7.1 Register Overview ......................................24 1.2 Applications .................................................. 4 7.2 Detailed Register Description .....................25 1.3 Block Diagram .. |
|
|
|
|
AMSCO |
Programmable PWM DC Motor Driver / Controller - - Programmable PWM DC Motor Driver / Controller with µP Interface (Three Wire Interface) Programmable Functions and Parameters for Motor Current, Voltage and Speed Regulation Single Voltage Supply in the range Vbat = 6.0 V to 18 V (Vbat,max = 30 |
|
|
|
|
ams |
Data Acquisition Device ........................................................................ 3 1.2 Applications .......................................................................................... 4 1.3 Block diagram ............................................... |
|
|
|
|
Alliance Semiconductor |
3.3V Synchronous SRAMS 3.3V I/O, burst counter, and Pipelined Outputs Commercial Temperature Ranges AS8C403601-QC166N AS8C401801-QC166N 403601/401801 403601/401801 403601/401801 NOVEMBER 1 AS8C403601, AS8C401801,128K x 36, 256K x 18, 3.3V Synchronous SRAMS with ZBT™ F |
|
|
|
|
Alliance Semiconductor |
3.3V Synchronous SRAMS 3.3V I/O, burst counter, and Pipelined Outputs Commercial Temperature Ranges AS8C403601-QC166N AS8C401801-QC166N 403601/401801 403601/401801 403601/401801 NOVEMBER 1 AS8C403601, AS8C401801,128K x 36, 256K x 18, 3.3V Synchronous SRAMS with ZBT™ F |
|
|
|
|
Alliance Semiconductor |
3.3V Synchronous SRAMS 3.3V I/O, burst counter, and Pipelined Outputs Commercial Temperature Ranges AS8C403601-QC166N AS8C401801-QC166N 403601/401801 403601/401801 403601/401801 NOVEMBER 1 AS8C403601, AS8C401801,128K x 36, 256K x 18, 3.3V Synchronous SRAMS with ZBT™ F |
|
|
|
|
Alliance Semiconductor |
3.3V Synchronous SRAMs ◆ ◆ AS8C403625 AS8C401825 Description TheAS8C403625/1825 are high-speed SRAMs organized as 128K x 36/256K x 18. The AS8C403625/1825 SRAMs contain write, data, address and control registers. There are no registers in the data output path (flow- |
|
|
|
|
Alliance Semiconductor |
3.3V Synchronous ZBT SRAMs Pin Description Summar y A0-A18 CE1, CE2, CE2 OE R/W CEN BW1, BW2, BW3, BW4 CLK ADV/ LD LBO ZZ I/O0-I/O31, I/OP1-I/OP4 VDD, V DDQ VSS Address Inputs Chip Enables Output Enable Read/Write S ignal Clock Enable Individual Byte Write Selects Clock Advan |
|
Desde 2024. D4U Semiconductor.
|