| No. | parte # | Fabricante | Descripción | Hoja de Datos |
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Zarlink Semiconductor |
Worldwide ADSL2+ Dual Channel Line Driver • Fixed Voltage Gain Of 13 • 450 mA Peak Output Drive Capability • ±5 V to ±12 V Dual Supplies Or 10 V to 24 V Single Supply • 44 Vp-p Differential Output Into a 100 Ω Load • 40.5 Vp-p Differential Output Into a 60 Ω Load • Low-power Disable Mode For |
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Zarlink Semiconductor Inc |
Synthesized Broadband Converter with Programmable Power • • Single chip synthesized broadband solution Configurable as both up converter and downconverter requirements in double conversion tuner applications Incorporates 8 programmable mixer power settings Compatible with digital and analogue system requi |
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Zarlink Semiconductor |
Cable Tuner Front End LNA • • • • • Single chip dual output LNA Wide dynamic range on both channels Independent AGC facility incorporated into all channel paths Independent disable facility incorporated into all channel paths Full ESD protection. (Normal ESD handling procedur |
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Zarlink Semiconductor Inc |
Dual stage IF amplifier • • • • • Single chip solution for tuner IF gain and AGC Contains 34 dB of AGC shared between two AGC stages Design optimised for high signal handling with low inter-modulation spurious generation I/O ports optimised to interface with standard SAW fil |
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Zarlink Semiconductor Inc |
Wide Dynamic Range Image Reject MOPLL • • • • • • • • • Single chip mixer/oscillator PLL combination for multi band tuner for DTT applications Each mixer oscillator band optimized for wide dynamic range RF input stages allow for either single-ended or differential drive PLL frequency syn |
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Zarlink Semiconductor |
Front End Power Splitter • Single chip quadruple power splitter (primary channel, secondary channel, OOB channel and loop through) Wide dynamic range on all channels Independent AGC facility incorporated into all channel paths CSO, CTB, CXM all better than -62dBc for +3dBmV |
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Zarlink Semiconductor |
1.3GHz Dual Wideband Logarithmic Amplifier s s s s s s 1.3GHz Bandwidth (-3dB) Balanced IF limiting 3ns Rise Times/5ns Fall Times (six stages) 20ns Pulse Handling (six stages) Temperature Stabilised Surface Mountable APPLICATIONS s s s Ultra Wideband Log Receivers Channelised Receivers Monop |
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Desde 2024. D4U Semiconductor.
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