| No. | parte # | Fabricante | Descripción | Hoja de Datos |
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Zarlink Semiconductor |
4/8/16 Port IMA/TC PHY Device IMA • • • • • Up to 16 T1, E1, J1, DSL links & up to 8 IMA groups with 1 to 16 links/IMA group1 Supports symmetrical & asymmetrical operation CTC (common transmit) & ITC (independent transmit) clocking modes Pre-processing of RX ICP (IMA control prot |
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Zarlink Semiconductor |
T1/E1 Synchronizer • • • • Supports AT&T TR62411 and Bellcore GR-1244CORE and Stratum 4 timing for DS1 interfaces Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing for E1 interfaces Selectable 19.44 MHz, 1.544MHz, 2.048MHz or 8kHz input reference signals Provi |
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Zarlink Semiconductor |
Programmable SLIC • • • • • • • • • Transformerless 2 W to 4 W conversion Controls battery feed to line Programmable line impedance Programmable network balance impedance Off-hook and dial pulse detection Ring ground over-current protection Programmable gain Programma |
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Zarlink Semiconductor |
(MT9160B / MT9161B) 5 Volt Multi-Featured Codec • • Improved idle channel noise over MT9160 MT9161 version features a delayed framing pulse in SSI and ST-BUS modes to facilitate cascaded devices Programmable µ-Law/A-Law Codec and Filters Programmable ITU-T G.711/sign-magnitude coding Programmable |
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Zarlink Semiconductor |
128-Channel Voice Echo Canceller • MT93L04 is a Multi-chip Module (MCM) consisting of 4 MT93L00 devices thus providing 128 channels of 64 msec Echo Cancellation Each device (MT93L00) is independent of the each other Each device has the capability of cancelling echo over 32 channels |
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Zarlink Semiconductor |
4/8/16 Port IMA/TC PHY Device IMA • • • • • Up to 16 T1, E1, J1, DSL links & up to 8 IMA groups with 1 to 16 links/IMA group1 Supports symmetrical & asymmetrical operation CTC (common transmit) & ITC (independent transmit) clocking modes Pre-processing of RX ICP (IMA control prot |
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Zarlink Semiconductor |
(MT90880 - MT90883) TDM to Packet Processors • • • • • • • • WAN interface, consisting of 32 input and output streams at 2.048 or 8.192 Mbs Up to 1024 bi-directional 64 Kbs channels N * 64 Kbs trunking of channels across any stream and channel 1 K by 1 K non-blocking TDM switch Local TDM interf |
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Zarlink Semiconductor |
Octal T1/E1/J1 Framer • • • • Eight fully independent, T1/E1/J1 framers 3.3 V supply with 5 V tolerant inputs Selectable 2.048 Mbit/s or 8.192 Mbit/s serial buses for both data and signaling Framing Modes: - T1: D4, ESF, T1DM - E1: Basic Framing, CRC4 multiframing and Sig |
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Zarlink Semiconductor |
T1/E1/OC3 System Synchronizer • Supports AT&T TR62411 and Bellcore GR-1244CORE Stratum 3, Stratum 4 Enhanced and Stratum 4 timing for DS1 interfaces • Supports ITU-T G.813 Option 1 clocks for 2048 kbit/s interfaces • Supports ITU-T G.812 Type IV clocks for 1,544 kbit/s interfaces |
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Zarlink Semiconductor |
(MT9160B / MT9161B) 5 Volt Multi-Featured Codec • • Improved idle channel noise over MT9160 MT9161 version features a delayed framing pulse in SSI and ST-BUS modes to facilitate cascaded devices Programmable µ-Law/A-Law Codec and Filters Programmable ITU-T G.711/sign-magnitude coding Programmable |
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Zarlink Semiconductor |
4/8/16 Port IMA/TC PHY Device IMA • • • • • Up to 16 T1, E1, J1, DSL links & up to 8 IMA groups with 1 to 16 links/IMA group1 Supports symmetrical & asymmetrical operation CTC (common transmit) & ITC (independent transmit) clocking modes Pre-processing of RX ICP (IMA control prot |
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Zarlink Semiconductor |
1023 Channel Voice Over IP/AAL2 Processor • 1023 full-duplex PCM or ADPCM voice channels over IP/UDP/RTP connections or over AAL2 VCs • Simultaneously support of IP/UDP connection and AAL2 VC • RTP packaging optional in IP/UDP connection • Supports IP version 4 and version 6 • Supports IP ov |
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Zarlink Semiconductor |
3.3V 10/100 Fast Ethernet Transceiver to MII Ordering Information G G G G G G G G G G G G G G G G G Integrated 10/100 Mbps Ethernet in a Single Chip Solution Single 3.3V Power Supply Half Duplex and Full Duplex in both 10BASE-T and 100BASE-TX Full MII for a Glueless MAC Connection Extended Reg |
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Zarlink Semiconductor |
(MT90880 - MT90883) TDM to Packet Processors • • • • • • • • WAN interface, consisting of 32 input and output streams at 2.048 or 8.192 Mbs Up to 1024 bi-directional 64 Kbs channels N * 64 Kbs trunking of channels across any stream and channel 1 K by 1 K non-blocking TDM switch Local TDM interf |
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Zarlink Semiconductor |
3V Large Digital Switch • • • • • • • • • • • • 2,048 × 2,048 channel non-blocking switching at 8.192 Mb/s Per-channel variable or constant throughput delay Automatic identification of ST-BUS/GCI interfaces Accept ST-BUS streams of 2.048, 4.096 or 8.192 Mb/s Automatic frame |
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Zarlink Semiconductor |
T1/E1 System Synchronizer with Holdover • Supports AT&T TR62411 and Bellcore GR-1244CORE, Stratum 4 Enhanced and Stratum 4 timing for DS1 interfaces Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing for E1 interfaces Selectable 19.44 MHz, 1.544 MHz, 2.048 MHz or 8kHz input referen |
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Zarlink Semiconductor |
T1/E1 System Synchronizer • Supports AT&T TR62411 and Bellcore GR-1244CORE, Stratum 4 Enhanced and Stratum 4 timing for DS1 interfaces Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing for E1 interfaces Selectable 19.44 MHz, 1.544MHz, 2.048MHz or 8kHz input reference |
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Zarlink Semiconductor |
Programmable Ringing SLIC • • • • • • • • • • • • • • • Transformerless 2W to 4W conversion Controls battery feed to line Programmable line impedance Programmable network balance impedance Off-hook and dial pulse detection Protects against GND short circuit Programmable gain |
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Zarlink Semiconductor |
E1 Single Chip Transceiver • Combined PCM 30 framer, Line Interface Unit (LIU) and link controllers in a 68 pin PLCC or 100 pin MQFP package Selectable bit rate data link access with optional Sa bits HDLC controller (HDLC0) and channel 16 HDLC controller (HDLC1) LIU dynamic ra |
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Zarlink Semiconductor |
Multi-Channel Voice Echo Canceller • Independent multiple channels of echo cancellation; from 32 channels of 64 ms to 16 channels of 128 ms with the ability to mix channels at 128 ms or 64 ms in any combination Independent Power Down mode for each group of 2 channels for power managem |
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Desde 2024. D4U Semiconductor.
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