No. | parte # | Fabricante | Descripción | Hoja de Datos |
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Xilinx |
Spartan-6 FPGA tical timing characteristics to the -3 speed grade. All supply voltage and junction temperature specifications are representative of worst-case conditions. The parameters included are common to popular designs and typical applications. This Spartan-6 |
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Xilinx |
Spartan-6 FPGA tical timing characteristics to the -3 speed grade. All supply voltage and junction temperature specifications are representative of worst-case conditions. The parameters included are common to popular designs and typical applications. This Spartan-6 |
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Xilinx |
Spartan-6 FPGA tical timing characteristics to the -3 speed grade. All supply voltage and junction temperature specifications are representative of worst-case conditions. The parameters included are common to popular designs and typical applications. This Spartan-6 |
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|
|
Xilinx |
Spartan-6 FPGA tical timing characteristics to the -3 speed grade. All supply voltage and junction temperature specifications are representative of worst-case conditions. The parameters included are common to popular designs and typical applications. This Spartan-6 |
|
|
|
Xilinx |
Spartan-6 FPGA tical timing characteristics to the -3 speed grade. All supply voltage and junction temperature specifications are representative of worst-case conditions. The parameters included are common to popular designs and typical applications. This Spartan-6 |
|
|
|
Xilinx |
Spartan-6 FPGA tical timing characteristics to the -3 speed grade. All supply voltage and junction temperature specifications are representative of worst-case conditions. The parameters included are common to popular designs and typical applications. This Spartan-6 |
|
|
|
Xilinx |
Spartan-6 FPGA tical timing characteristics to the -3 speed grade. All supply voltage and junction temperature specifications are representative of worst-case conditions. The parameters included are common to popular designs and typical applications. This Spartan-6 |
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XILINX |
Virtex-6 CXT • Advanced, high-performance, FPGA Logic • Real 6-input look-up table (LUT) technology • Dual LUT5 (5-input LUT) option • LUT/dual flip-flop pair for applications requiring rich register mix • Improved routing efficiency • 64-bit (or 32 x 2-bit) dis |
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Xilinx |
Spartan-6 FPGA tical timing characteristics to the -3 speed grade. All supply voltage and junction temperature specifications are representative of worst-case conditions. The parameters included are common to popular designs and typical applications. This Spartan-6 |
|
|
|
XILINX |
Virtex-6 CXT • Advanced, high-performance, FPGA Logic • Real 6-input look-up table (LUT) technology • Dual LUT5 (5-input LUT) option • LUT/dual flip-flop pair for applications requiring rich register mix • Improved routing efficiency • 64-bit (or 32 x 2-bit) dis |
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XILINX |
Virtex-6 CXT • Advanced, high-performance, FPGA Logic • Real 6-input look-up table (LUT) technology • Dual LUT5 (5-input LUT) option • LUT/dual flip-flop pair for applications requiring rich register mix • Improved routing efficiency • 64-bit (or 32 x 2-bit) dis |
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|
|
XILINX |
Virtex-6 CXT • Advanced, high-performance, FPGA Logic • Real 6-input look-up table (LUT) technology • Dual LUT5 (5-input LUT) option • LUT/dual flip-flop pair for applications requiring rich register mix • Improved routing efficiency • 64-bit (or 32 x 2-bit) dis |
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