Xilinx XC1 Hoja de datos

No.	parte #	Fabricante	Descripción
1	XC17S15A	Xilinx	Spartan-II/Spartan-IIE Family OTP Configuration PROMs • Configuration one-time programmable (OTP) read-only memory designed to store configuration bitstreams for Spartan™-II/Spartan-IIE FPGA devices • Simple interface to the Spartan device • Programmable reset polarity (active High or active Low) • Low-
2	X17256128DD8M	Xilinx Inc	QPRO Family of XC1700D QML Configuration PROMs • • • Certified to MIL-PRF-38535 Appendix A QML (Qualified Manufacturer Listing.) Also available under the following Standard Microcircuit Drawings (SMD): 5962-94717 and 5962-95617. Configuration one-time programmable (OTP) read-only memory designed
3	X1725636DD8B	Xilinx Inc	QPRO Family of XC1700D QML Configuration PROMs • • • Certified to MIL-PRF-38535 Appendix A QML (Qualified Manufacturer Listing.) Also available under the following Standard Microcircuit Drawings (SMD): 5962-94717 and 5962-95617. Configuration one-time programmable (OTP) read-only memory designed
4	X1725636DD8M	Xilinx Inc	QPRO Family of XC1700D QML Configuration PROMs • • • Certified to MIL-PRF-38535 Appendix A QML (Qualified Manufacturer Listing.) Also available under the following Standard Microcircuit Drawings (SMD): 5962-94717 and 5962-95617. Configuration one-time programmable (OTP) read-only memory designed
5	X1725665DD8M	Xilinx Inc	QPRO Family of XC1700D QML Configuration PROMs • • • Certified to MIL-PRF-38535 Appendix A QML (Qualified Manufacturer Listing.) Also available under the following Standard Microcircuit Drawings (SMD): 5962-94717 and 5962-95617. Configuration one-time programmable (OTP) read-only memory designed
6	XC18V01	Xilinx	In-System Programmable Configuration PROMs • In-System Programmable 3.3V PROMs for Configuration of Xilinx FPGAs ♦ Endurance of 20,000 Program/Erase Cycles ♦ Program/Erase Over Full Industrial Voltage and Temperature Range ( –40°C to +85°C) • IEEE Std 1149.1 Boundary-Scan (JTAG) Support • JTAG
7	XC17S50A	Xilinx	Spartan-II/Spartan-IIE Family OTP Configuration PROMs • Configuration one-time programmable (OTP) read-only memory designed to store configuration bitstreams for Spartan™-II/Spartan-IIE FPGA devices • Simple interface to the Spartan device • Programmable reset polarity (active High or active Low) • Low-
8	XC17S100A	Xilinx	Spartan-II/Spartan-IIE Family OTP Configuration PROMs • Configuration one-time programmable (OTP) read-only memory designed to store configuration bitstreams for Spartan™-II/Spartan-IIE FPGA devices • Simple interface to the Spartan device • Programmable reset polarity (active High or active Low) • Low-
9	X17256128DD8B	Xilinx Inc	QPRO Family of XC1700D QML Configuration PROMs • • • Certified to MIL-PRF-38535 Appendix A QML (Qualified Manufacturer Listing.) Also available under the following Standard Microcircuit Drawings (SMD): 5962-94717 and 5962-95617. Configuration one-time programmable (OTP) read-only memory designed
10	X17256256DD8B	Xilinx Inc	QPRO Family of XC1700D QML Configuration PROMs • • • Certified to MIL-PRF-38535 Appendix A QML (Qualified Manufacturer Listing.) Also available under the following Standard Microcircuit Drawings (SMD): 5962-94717 and 5962-95617. Configuration one-time programmable (OTP) read-only memory designed
11	X17256256DD8M	Xilinx Inc	QPRO Family of XC1700D QML Configuration PROMs • • • Certified to MIL-PRF-38535 Appendix A QML (Qualified Manufacturer Listing.) Also available under the following Standard Microcircuit Drawings (SMD): 5962-94717 and 5962-95617. Configuration one-time programmable (OTP) read-only memory designed
12	X1725665DD8B	Xilinx Inc	QPRO Family of XC1700D QML Configuration PROMs • • • Certified to MIL-PRF-38535 Appendix A QML (Qualified Manufacturer Listing.) Also available under the following Standard Microcircuit Drawings (SMD): 5962-94717 and 5962-95617. Configuration one-time programmable (OTP) read-only memory designed
13	XC1700E	Xilinx	Configuration PROMs • One-time programmable (OTP) read-only memory designed to store configuration bitstreams of Xilinx® FPGAs • Simple interface to the FPGA; requires only one user I/O pin • Cascadable for storing longer or multiple bitstreams • Programmable reset pola
14	XC1700EL	Xilinx	Configuration PROMs • One-time programmable (OTP) read-only memory designed to store configuration bitstreams of Xilinx® FPGAs • Simple interface to the FPGA; requires only one user I/O pin • Cascadable for storing longer or multiple bitstreams • Programmable reset pola
15	XC17512L	Xilinx	Configuration PROMs • One-time programmable (OTP) read-only memory designed to store configuration bitstreams of Xilinx® FPGAs • Simple interface to the FPGA; requires only one user I/O pin • Cascadable for storing longer or multiple bitstreams • Programmable reset pola
16	XC1765D	Xilinx	QML Configuration PROMs • Certified to MIL-PRF-38535 Appendix A QML (Qualified Manufacturer Listing) • Also available under the following Standard Microcircuit Drawings (SMD): 5962-94717 and 5962-95617 • Configuration one-time programmable (OTP) read-only memory designed to
17	XC17S30A	Xilinx	Spartan-II/Spartan-IIE Family OTP Configuration PROMs • Configuration one-time programmable (OTP) read-only memory designed to store configuration bitstreams for Spartan™-II/Spartan-IIE FPGA devices • Simple interface to the Spartan device • Programmable reset polarity (active High or active Low) • Low-
18	TMSH	Xilinx Inc	XC1800 Series of In-System Programmable Configuration PROMs • In-system programmable 3.3V PROMs for configuration of Xilinx FPGAs - Endurance of 10,000 program/erase cycles - Program/erase over full commercial voltage and temperature range IEEE Std 1149.1 boundary-scan (JTAG) support Simple interface to the F
19	TDOZX	Xilinx Inc	XC1800 Series of In-System Programmable Configuration PROMs • In-system programmable 3.3V PROMs for configuration of Xilinx FPGAs - Endurance of 10,000 program/erase cycles - Program/erase over full commercial voltage and temperature range IEEE Std 1149.1 boundary-scan (JTAG) support Simple interface to the F
20	17512LJC	Xilinx	XC17512LJC • One-time programmable (OTP) read-only memory designed to store configuration bitstreams of Xilinx FPGA devices Simple interface to the FPGA; requires only one user I/O pin Cascadable for storing longer or multiple bitstreams Programmable reset pola