No. | parte # | Fabricante | Descripción | Hoja de Datos |
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White Electronic |
DUAL KEY DIMM 4x512Kx72 Synchronous, Synchronous Burst Pipeline Architecture; Single Cycle Deselect Linear and Sequential Burst Support via MODE pin Clock Controlled Registered Module Enable (EM#) Clock Controlled Registered Bank Enables (E1#, E2#, E3#, E4#) Clock |
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White Electronic |
512Kx32 Synchronous Pipeline Burst SRAM s Fast clock speed: 200, 166, 150 & 133MHz s Fast access times: 2.5ns, 3.5ns, 3.8ns & 4.0ns s Fast OE access times: 2.5ns, 3.5ns, 3.8ns 4.0ns s Single +3.3V power supply (VDD) s Separate +3.3V or +2.5V isolated output buffer supply (VDDQ) s Snooze Mo |
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White Electronic |
DUAL KEY DIMM 4x512Kx72 Synchronous Burst Pipeline Architecture; Dual Cycle Deselect Linear and Sequential Burst Support via MODE pin Clock Controlled Registered Module Enable (EM#) Clock Controlled Registered Bank Enables (E1#, E2#, E3#, E4#) Clock Controlled Byt |
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White Electronic Designs |
4M x 72 SDRAM Package: 219 Plastic Ball Grid Array (PBGA), 25 x 21mm Single 3.3V ±0.3V power supply Fully Synchronous; all signals registered on positive edge of system clock cycle Internal pipelined operation; column address can be changed |
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White Electronic Designs |
32MB - 4Mx64 SDRAM PC100 and PC133 compatible Burst Mode Operation Auto and Self Refresh capability LVTTL compatible inputs and outputs Serial Presence Detect with EEPROM Fully synchronous: All signals are registered on the positive edge of the system |
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White Electronic Designs |
512MB - 64Mx64 SDRAM UNBUFFERED PC100 and PC133 compatible Burst Mode Operation Auto and Self Refresh capability LVTTL compatible inputs and outputs Serial Presence Detect with EEPROM Fully synchronous: All signals are registered on the positive edge of the system clock Programmabl |
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White Electronic Designs |
512MB -64Mx64 SDRAM UNBUFFERED PC100 and PC133 compatible Burst Mode Operation Auto and Self Refresh capability LVTTL compatible inputs and outputs Serial Presence Detect with EEPROM Fully synchronous: All signals are registered on the positive edge of the system clock Programmabl |
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White Electronic Designs |
SDRAM UNBUFFERED PC100 and PC133 compatible Burst Mode Operation Auto and Self Refresh capability LVTTL compatible inputs and outputs Serial Presence Detect with EEPROM Fully synchronous: All signals are registered on the positive edge of the system clock Programmabl |
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White Electronic Designs |
SDRAM UNBUFFERED n Burst Mode Operation n Auto and Self Refresh capability n LVTTL compatible inputs and outputs n Serial Presence Detect with EEPROM n Fully synchronous: All signals are registered on the positive edge of the system clock n Programmable Burst Lengths |
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White Electronic Designs |
512MB - 2x32Mx72 SDRAM Burst Mode Operation Auto and Self Refresh capability LVTTL compatible inputs and outputs Serial Presence Detect with EEPROM Fully synchronous: All signals are registered on the positive edge of the system clock Programmable Burst Lengths: 1, 2, 4, 8 |
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White Electronic Designs |
8Mx72 SDRAM UNBUFFERED Burst Mode Operation Auto and Self Refresh capability LVTTL compatible inputs and outputs Serial Presence Detect with EEPROM Fully synchronous: All signals are registered on the positive edge of the system clock Programmable Burst Lengths: 1, 2, 4, 8 |
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White Electronic Designs Corporation |
1GB - 128M X 64 SDRAM Unbuffered n Burst Mode Operation n Auto and Self Refresh capability n LVTTL compatible inputs and outputs n Serial Presence Detect with EEPROM n Fully synchronous: All signals are registered on the positive edge of the system clock n Programmable Burst Lengths |
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White Electronic Designs Corporation |
1GB - 128M X 64 SDRAM Unbuffered n PC100 and PC133 compatible n Burst Mode Operation n Auto and Self Refresh capability n LVTTL compatible inputs and outputs n Serial Presence Detect with EEPROM n Fully synchronous: All signals are registered on the positive edge of the system clock |
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White Electronic Designs Corporation |
RISC MICROPROCESSOR MULTI-CHIP PACKAGE doze, nap, sleep and dynamic power management. The WED3C755E8M-XBX multichip package consists of: 755 RISC processor (E die revision) Dedicated 1MB SSRAM L2 cache, configured as 128Kx72 21mmx25mm, 255 Ceramic Ball Grid Array (CBGA) Core Frequency/L2 |
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White Electronic Designs Corporation |
128MB - 16Mx64 SDRAM UNBUFFERED Burst Mode Operation Auto and Self Refresh capability LVTTL compatible inputs and outputs Serial Presence Detect with EEPROM Fully synchronous: All signals are registered on the positive edge of the system clock Programmable Burst Lengths: 1, 2, 4, 8 |
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White Electronic Designs Corporation |
SDRAM UNBUFFERED PC100 and PC133 compatible Burst Mode Operation Auto and Self Refresh capability LVTTL compatible inputs and outputs Serial Presence Detect with EEPROM Fully synchronous: All signals are registered on the positive edge of the system clock Programmabl |
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White Electronic Designs |
4M x 64 SDRAM High Frequency = 100, 125, 133MHz Package: • 219 Plastic Ball Grid Array (PBGA), 21 x 21mm Single 3.3V ±0.3V power supply Fully Synchronous; all signals registered on positive edge of system clock cycle Internal pipelined operation; column address ca |
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White Electronic |
DUAL KEY DIMM SRAM MODULE 4x512Kx72 Synchronous, Synchronous Burst Flow-Through Architecture Linear and Sequential Burst Support via MODE pin Clock Controlled Registered Module Enable (EM#) Clock Controlled Registered Bank Enables (E1#, E2#, E3#, E4#) Clock Controlled Byte Wr |
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White Electronic |
Synchronous Pipeline Burst NBL SRAM Fast clock speed: 250, 225, 200, 166, 150, 133MHz Fast access times: 2.6, 2.8, 3.0, 3.5, 3.8, 4.2ns Fast OE# access times: 2.6, 2.8, 3.0, 3.5, 3.8, 4.2ns Separate +2.5V ± 5% power supplies for Core, I/O (VCC, VCCQ) Snooze Mode for |
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White Electronic |
Synchronous Pipeline Burst NBL SRAM Fast clock speed: 166, 150, 133, and 100MHz Fast access times: 3.5ns, 3.8ns, 4.2ns, and 5.0ns Fast OE# access times: 3.5ns, 3.8ns, 4.2ns, and 5.0ns Single +3.3V ± 5% power supply (VCC) Snooze Mode for reduced-standby power Individual Byte Write contr |
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