No. | parte # | Fabricante | Descripción | Hoja de Datos |
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White Electronic Designs |
4M x 72 SDRAM Package: 219 Plastic Ball Grid Array (PBGA), 25 x 21mm Single 3.3V ±0.3V power supply Fully Synchronous; all signals registered on positive edge of system clock cycle Internal pipelined operation; column address can be changed |
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White Electronic Designs |
32MB - 4Mx64 SDRAM PC100 and PC133 compatible Burst Mode Operation Auto and Self Refresh capability LVTTL compatible inputs and outputs Serial Presence Detect with EEPROM Fully synchronous: All signals are registered on the positive edge of the system |
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White Electronic Designs |
512MB - 64Mx64 SDRAM UNBUFFERED PC100 and PC133 compatible Burst Mode Operation Auto and Self Refresh capability LVTTL compatible inputs and outputs Serial Presence Detect with EEPROM Fully synchronous: All signals are registered on the positive edge of the system clock Programmabl |
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White Electronic Designs |
512MB -64Mx64 SDRAM UNBUFFERED PC100 and PC133 compatible Burst Mode Operation Auto and Self Refresh capability LVTTL compatible inputs and outputs Serial Presence Detect with EEPROM Fully synchronous: All signals are registered on the positive edge of the system clock Programmabl |
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White Electronic Designs |
SDRAM UNBUFFERED PC100 and PC133 compatible Burst Mode Operation Auto and Self Refresh capability LVTTL compatible inputs and outputs Serial Presence Detect with EEPROM Fully synchronous: All signals are registered on the positive edge of the system clock Programmabl |
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White Electronic Designs |
SDRAM UNBUFFERED n Burst Mode Operation n Auto and Self Refresh capability n LVTTL compatible inputs and outputs n Serial Presence Detect with EEPROM n Fully synchronous: All signals are registered on the positive edge of the system clock n Programmable Burst Lengths |
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White Electronic Designs |
512MB - 2x32Mx72 SDRAM Burst Mode Operation Auto and Self Refresh capability LVTTL compatible inputs and outputs Serial Presence Detect with EEPROM Fully synchronous: All signals are registered on the positive edge of the system clock Programmable Burst Lengths: 1, 2, 4, 8 |
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White Electronic Designs |
8Mx72 SDRAM UNBUFFERED Burst Mode Operation Auto and Self Refresh capability LVTTL compatible inputs and outputs Serial Presence Detect with EEPROM Fully synchronous: All signals are registered on the positive edge of the system clock Programmable Burst Lengths: 1, 2, 4, 8 |
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White Electronic Designs Corporation |
1GB - 128M X 64 SDRAM Unbuffered n Burst Mode Operation n Auto and Self Refresh capability n LVTTL compatible inputs and outputs n Serial Presence Detect with EEPROM n Fully synchronous: All signals are registered on the positive edge of the system clock n Programmable Burst Lengths |
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White Electronic Designs Corporation |
1GB - 128M X 64 SDRAM Unbuffered n PC100 and PC133 compatible n Burst Mode Operation n Auto and Self Refresh capability n LVTTL compatible inputs and outputs n Serial Presence Detect with EEPROM n Fully synchronous: All signals are registered on the positive edge of the system clock |
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White Electronic Designs Corporation |
RISC MICROPROCESSOR MULTI-CHIP PACKAGE doze, nap, sleep and dynamic power management. The WED3C755E8M-XBX multichip package consists of: 755 RISC processor (E die revision) Dedicated 1MB SSRAM L2 cache, configured as 128Kx72 21mmx25mm, 255 Ceramic Ball Grid Array (CBGA) Core Frequency/L2 |
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White Electronic Designs Corporation |
128MB - 16Mx64 SDRAM UNBUFFERED Burst Mode Operation Auto and Self Refresh capability LVTTL compatible inputs and outputs Serial Presence Detect with EEPROM Fully synchronous: All signals are registered on the positive edge of the system clock Programmable Burst Lengths: 1, 2, 4, 8 |
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White Electronic Designs Corporation |
SDRAM UNBUFFERED PC100 and PC133 compatible Burst Mode Operation Auto and Self Refresh capability LVTTL compatible inputs and outputs Serial Presence Detect with EEPROM Fully synchronous: All signals are registered on the positive edge of the system clock Programmabl |
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White Electronic Designs |
4M x 64 SDRAM High Frequency = 100, 125, 133MHz Package: • 219 Plastic Ball Grid Array (PBGA), 21 x 21mm Single 3.3V ±0.3V power supply Fully Synchronous; all signals registered on positive edge of system clock cycle Internal pipelined operation; column address ca |
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White Electronic Designs |
Asynchronous SRAM n 256Kx24 bit CMOS Static n Random Access Memory Array Fast Access Times: 10, 12, and 15ns Master Output Enable and Write Control TTL Compatible Inputs and Outputs Fully Static, No Clocks n Surface Mount Package 119 Lead BGA (JEDEC MO-163), |
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White Electronic Designs |
Asynchronous SRAM n 256Kx24 bit CMOS Static n Random Access Memory Array Fast Access Times: 10, 12, and 15ns Master Output Enable and Write Control Three Chip Enables for Byte Control TTL Compatible Inputs and Outputs Fully Static, No Clocks n Surface Mount |
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White Electronic Designs |
Asynchronous SRAM 512Kx24 bit CMOS Static Random Access Memory Array Fast Access Times: 10, 12, and 15ns Master Output Enable and Write Control TTL Compatible Inputs and Outputs Fully Static, No Clocks 119 Lead BGA (JEDEC MO-163), No. 391 Small |
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White Electronic Designs |
Asynchronous SRAM DESCRIPTION n n 512Kx24 bit CMOS Static Random Access Memory Array • Fast Access Times: 10, 12, and 15ns • Master Output Enable and Write Control • Three Chip Enables for Byte Control • TTL Compatible Inputs and Outputs • Fully Static, No Clocks T |
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White Electronic Designs |
8Mx72 Synchronous DRAM + 16Mb Flash Mixed Module Multi-Chip Package n n Sector Architecture Package: • 275 Plastic Ball Grid Array (PBGA), 32mm x 25mm •One 16KByte, two 8KBytes, one 32KByte, and fifteen 64KBytes in byte mode •One 8K word, two 4K words, one 16K word, and fifteen 32K word sectors in word mode. •Any c |
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White Electronic Designs |
RISC Microprocessor doze, nap, sleep and dynamic power management. The WED3C7410E16M-400BX multichip package consists of: • 7410E AltiVec RISC processor • Dedicated 2MB SSRAM L2 cache, configured as 256Kx72 • 21mmx25mm, 255 Ceramic Ball Grid Array (CBGA) • Maximum Cor |
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