No. | parte # | Fabricante | Descripción | Hoja de Datos |
---|---|---|---|---|
|
|
VIA |
OCI North Bridge list to reflect Apollo VPX • Added pinouts, electrical, and mechanical specs from 580VP data sheet • Added tables of pins in alphabetical order for both chips • Changed pinouts to reflect VPX - Removed UMA (added CPURSTI and CPURSTO on MREQ0/1#) - Ad |
|
|
|
VIA |
Bringing Serial ATA/RAID native Serial RAID solution to be integrated into PC chipset architecture g g g n Ease of Use g g Supports RAID Levels 0, 1, 0+11 and JBOD Highest HDD Data Transfer Rates for Maximum System Performance Superior Fault Tolerance for Optimum Data I |
|
|
|
VIA |
Real Time Clock • Drop-in replacement for IBM AT computer clock/calendar. • Pin configuration closely matches the DS12887 • Totally nonvolatile with over 10 years of operation in the absence of power · Self-contained subsystem includes lithium, quartz and support ci |
|
|
|
VIA |
KT133A AMD ATHLON NORTH BRIDGE & 97& 97& 97& 97&093 97&$ 97&$ 97& 97&$ 97&; 97 97 97 97 97 97 0RELOH 6RXWK 6XSHU 6RXWK $SROOR 93 $SROOR 93; $SROOR 93 $SROOR 93 $SROOR 093 $SROOR |
|
|
|
VIA |
Version CD South Bridge ................................................................................................................................................................... 1 OVERVIEW............................................................................ |
|
|
|
VIA |
Super South / South Bridge bullets, and overview Removed external APIC support, added IRQ0 input & internal THRM# output Updated pin descriptions: MCCS# (U5/U8 select), GPI3, GPI10, GPI11, GPO6, GPO10, GPO11, GPO21, GPIOC, GPIOD, CHAS, ATEST, THRM, LID Updated bit descriptions |
|
|
|
VIA |
KT133 Athlon North Bridge 7HFKQRORJLHV ,QF 'HOLYHULQJ 9DOXH KT133 - VT8363 • Full Featured Accelerated Graphics Port (AGP) Controller − Synchronous and pseudo-synchronous with the host CPU bus with optimal skew control − − − − − − − − − − − PCI AGP CPU Mode 33 MHz 66 MH |
|
|
|
VIA |
Green Pentium/P54C PCI/ISA System ........................................................................................................ 1 OVERVIEW........................................................................................................ 4 FUNCTIONAL DESCRIPTION ..... |
|
|
|
VIA |
PCI SUPER-I/O INTEGRATED PERIPHERAL CONTROLLER bullets, pin typos, ROMCS# description, f0Rx8, f4Rx2 Fixed block diagram, pinouts, register descriptions and electrical specs Fixed GPIO, PCS/MCCS, DRQ/DACK#, DACK IRQ option, FDC on LPT Fixed SuperIO RxF0-1,F6; FDCIObase+1,Fn0Rx43,59,5B-C,68,74-7F,8 |
|
|
|
VIA Technologies |
Real Time Clocks • Drop-in replacement for IBM AT computer clock/calendar. • Pin configuration closely matches the DS12887, DS12885and DS12885Q • Counts seconds, minutes, hours, days, day of the week, date, month, and year with leap year compensation www.DataSheet4U. |
|
|
|
VIA |
V-LINK CLIENT HIGHLY INTEGRATED SOUTH BRIDGE ................................................................................................................................................................... 1 OVERVIEW ........................................................................... |
|
|
|
Via |
Single-Chip SMA North Bridge ................................................................................................................................................................... 1 OVERVIEW ........................................................................... |
|
|
|
Via |
Slot-1 / Socket-370 PCI North Bridge list, overview, and vblock diagram from product brief 12/16/98 Updated pinouts to match engineering rev 0.5 document dated 12/1/98 DH 1/20/99 Updated pinouts to match engineering rev 0.8 document dated 12/22/98 DH 6/4/99 Added 133 MHz Support to Feat |
|
|
|
VIA Technologies |
Apollo Pro 66/100 MHZ Single-chip Socket-8/slot-1 North Bridge bullets Fixed GTLREF pin number in pin descriptions Moved strapping options from HA to MECC (PCLK description, Rx68-69) Updated register and bit definitions: Added Rx2C Subsystem Vendor ID and Rx2E Subsystem ID Added clarifying note on Rx50[7] Redefi |
|
|
|
VIA |
LCD bullets Fixed placement diagram in pin descriptions Fixed typo in pinout section footer Changed pin AC4 from SUSCLK to PCKRUN# Added DCLKRD function to pin AB22 (MAA14) Updated function 0 registers Rx50[5,3-1], 51[5,2-1], 53[5-3, 67-64[2], 69[75,1], |
|
|
|
Via |
Single-Chip Socket-370 PCI North Bridge ......................................................................................................................................................................1 SYSTEM OVERVIEW................................................................... |
|
|
|
Via |
Single-Chip SMA North Bridge ................................................................................................................................................................... 1 OVERVIEW............................................................................ |
|