No. | parte # | Fabricante | Descripción | Hoja de Datos |
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Vanguard International Semiconductor |
128Mb SDRAM ITEM tCLK tRAS tRCD tAC tRC Icc1 Clock Cycle Time (Min.) CL=2 CL=3 -7 7ns 45ns CL=2 CL=3 V28S20D 20ns 5.4ns 63ns 85mA 85mA 85mA 1mA P2V28S20/30/40ATP -75 -8 10ns 7.5ns 45ns 20ns 6ns 5.4ns 67.5ns 85mA 85mA 85mA 1mA 10ns 8ns 48ns 20ns 6ns 6ns 70ns 85 |
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Vanguard International Semiconductor |
CMOS Synchronous Dynamic RAM • Single 3.3V ( ± 0.3V ) power supply • High speed clock cycle time -7H: 133MHz<2-2-2>, -7L: 133MHz<3-3-3>, -8H: 100MHz<2-2-2> • Fully synchronous operation referenced to clock rising edge • Possible to assert random column access in every cycle • Qu |
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Vanguard International Semiconductor |
CMOS Synchronous Dynamic RAM • Single 3.3V ( ± 0.3V) power supply • High speed clock cycle time : 7.5ns/10ns • Fully synchronous with all signals referenced to a positive clock edge • Programmable CAS Iatency (2,3) • Programmable burst length (1,2,4,8,& Full page) • Programmabl |
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Vanguard International Semiconductor |
CMOS Synchronous Dynamic RAM • Single 3.3V ( ± 0.3V ) power supply • High speed clock cycle time -7H: 133MHz<2-2-2>, -7L: 133MHz<3-3-3>, -8H: 100MHz<2-2-2> • Fully synchronous operation referenced to clock rising edge • Possible to assert random column access in every cycle • Qu |
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Vanguard International Semiconductor |
16Mb CMOS Synchronous Dynamic RAM • Single 3.3V +/- 0.3V power supply • Clock Frequency: 180MHz, 166MHz, 143MHz, 125MHz, 100MHz • Fully synchronous with all signals referenced to a positive clock edge • Programmable CAS Iatency (2,3) • Programmable burst length (1,2,4,8,& Full page) |
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Vanguard International Semiconductor |
16Mb CMOS Synchronous Dynamic RAM • Single 3.3V( ± 0.3V ) power supply • Clock Frequency:100MHz • Fully synchronous with all signals referenced to a positive clock edge • Programmable CAS Iatency (2,3) • Programmable burst length (1,2,4,8,& Full page) • Programmable wrap sequence (S |
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Vanguard International Semiconductor |
CMOS Synchronous Dynamic RAM • Single 3.3V ( ± 0.3V ) power supply • High speed clock cycle time : 8/10 for LVTTL • High speed clock cycle time : 8/10 for SSTL - 3 • Fully synchronous with all signals referenced to a positive clock edge • Programmable CAS Iatency (2,3) • Program |
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Vanguard International Semiconductor |
CMOS Synchronous Dynamic RAM • Single 3.3V ( ± 0.3V ) power supply • High speed clock cycle time : 8/10ns • Fully synchronous with all signals referenced to a positive clock edge • Programmable CAS Iatency (2,3) • Programmable burst length (1,2,4,8,&Full page) • Programmable wra |
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Vanguard International Semiconductor |
CMOS Synchronous Dynamic RAM • Single 3.3V ( ± 0.3V ) power supply • High speed clock cycle time : 7/8ns • Fully synchronous with all signals referenced to a positive clock edge • Programmable CAS Iatency (2,3) • Programmable burst length (1,2,4,8,& Full page) • Programmable wra |
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Vanguard International Semiconductor |
128Mb SDRAM ITEM tCLK tRAS tRCD tAC tRC Icc1 Clock Cycle Time (Min.) CL=2 CL=3 -7 7ns 45ns CL=2 CL=3 V28S20D 20ns 5.4ns 63ns 85mA 85mA 85mA 1mA P2V28S20/30/40ATP -75 -8 10ns 7.5ns 45ns 20ns 6ns 5.4ns 67.5ns 85mA 85mA 85mA 1mA 10ns 8ns 48ns 20ns 6ns 6ns 70ns 85 |
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Vanguard International Semiconductor |
128Mb SDRAM ITEM tCLK tRAS tRCD tAC tRC Icc1 Clock Cycle Time (Min.) CL=2 CL=3 -7 7ns 45ns CL=2 CL=3 V28S20D 20ns 5.4ns 63ns 85mA 85mA 85mA 1mA P2V28S20/30/40ATP -75 -8 10ns 7.5ns 45ns 20ns 6ns 5.4ns 67.5ns 85mA 85mA 85mA 1mA 10ns 8ns 48ns 20ns 6ns 6ns 70ns 85 |
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Vanguard International Semiconductor |
128Mb SDRAM ITEM tCLK tRAS tRCD tAC tRC Icc1 Clock Cycle Time (Min.) CL=2 CL=3 -7 7ns 45ns CL=2 CL=3 V28S20D 20ns 5.4ns 63ns 85mA 85mA 85mA 1mA P2V28S20/30/40ATP -75 -8 10ns 7.5ns 45ns 20ns 6ns 5.4ns 67.5ns 85mA 85mA 85mA 1mA 10ns 8ns 48ns 20ns 6ns 6ns 70ns 85 |
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Vanguard International Semiconductor |
128Mb SDRAM ITEM tCLK tRAS tRCD tAC tRC Icc1 Clock Cycle Time (Min.) CL=2 CL=3 -7 7ns 45ns CL=2 CL=3 V28S20D 20ns 5.4ns 63ns 85mA 85mA 85mA 1mA P2V28S20/30/40ATP -75 -8 10ns 7.5ns 45ns 20ns 6ns 5.4ns 67.5ns 85mA 85mA 85mA 1mA 10ns 8ns 48ns 20ns 6ns 6ns 70ns 85 |
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Vanguard International Semiconductor |
128Mb SDRAM ITEM tCLK tRAS tRCD tAC tRC Icc1 Clock Cycle Time (Min.) CL=2 CL=3 -7 7ns 45ns CL=2 CL=3 V28S20D 20ns 5.4ns 63ns 85mA 85mA 85mA 1mA P2V28S20/30/40ATP -75 -8 10ns 7.5ns 45ns 20ns 6ns 5.4ns 67.5ns 85mA 85mA 85mA 1mA 10ns 8ns 48ns 20ns 6ns 6ns 70ns 85 |
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Vanguard International Semiconductor |
128Mb SDRAM ITEM tCLK tRAS tRCD tAC tRC Icc1 Clock Cycle Time (Min.) CL=2 CL=3 -7 7ns 45ns CL=2 CL=3 V28S20D 20ns 5.4ns 63ns 85mA 85mA 85mA 1mA P2V28S20/30/40ATP -75 -8 10ns 7.5ns 45ns 20ns 6ns 5.4ns 67.5ns 85mA 85mA 85mA 1mA 10ns 8ns 48ns 20ns 6ns 6ns 70ns 85 |
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Vanguard International Semiconductor |
CMOS Synchronous Dynamic RAM • Single 3.3V ( ± 0.3V) power supply • High speed clock cycle time : 7.5ns/10ns • Fully synchronous with all signals referenced to a positive clock edge • Programmable CAS Iatency (2,3) • Programmable burst length (1,2,4,8,& Full page) • Programmabl |
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Vanguard International Semiconductor |
CMOS Synchronous Dynamic RAM • Single 3.3V ( ± 0.3V ) power supply • High speed clock cycle time -7H: 133MHz<2-2-2>, -7L: 133MHz<3-3-3>, -8H: 100MHz<2-2-2> • Fully synchronous operation referenced to clock rising edge • Possible to assert random column access in every cycle • Qu |
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Vanguard International Semiconductor |
CMOS Synchronous Dynamic RAM • Single 3.3V ( ± 0.3V) power supply • High speed clock cycle time : 7.5ns/10ns • Fully synchronous with all signals referenced to a positive clock edge • Programmable CAS Iatency (2,3) • Programmable burst length (1,2,4,8,& Full page) • Programmabl |
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Vanguard International Semiconductor |
CMOS Synchronous Dynamic RAM • Single 3.3V ( ± 0.3V) power supply • High speed clock cycle time : 7.5ns/10ns • Fully synchronous with all signals referenced to a positive clock edge • Programmable CAS Iatency (2,3) • Programmable burst length (1,2,4,8,& Full page) • Programmabl |
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Vanguard International Semiconductor |
CMOS Synchronous Dynamic RAM • Single 3.3V ( ± 0.3V) power supply • High speed clock cycle time : 7.5ns/10ns • Fully synchronous with all signals referenced to a positive clock edge • Programmable CAS Iatency (2,3) • Programmable burst length (1,2,4,8,& Full page) • Programmabl |
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