No. | parte # | Fabricante | Descripción | Hoja de Datos |
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UMC |
4K x 1 High Speed NMOS SRAM • 45 ns maximum access time • No clocks or strobes required • Automatic CE power down • Identical cycle and access times • Single +5V supply (± 10%) • Pinout and function compatible to SY2147 • Total TTL compatible: All inputs and outputs • Separate |
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UMC |
1K x 4 High Speed NMOS SRAM • 45 ns maximum address access • Fully static operation: No clocks or strobes required • Fast chip select access time: 20ns max. • Identical cycle and access times • Single +5V supply • Industry standard 2114 pinout • Totally TTL compatible: All inp |
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UMC |
1K x 4 High Speed NMOS SRAM • 45 ns maximum access time • No cloS;ks or strobes required • Automatic CE power down • Identical cycle and access times • Single+5V supply (± 10%) • Pinout and function compatible to SY2148 • Industry standard 2114 pinout • Totally TTL compatible |
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UMC |
16K x 8 NMOS ROM • EPROM pin compatible • 16,384 x 8 bit organization • single +5 volt supply • Access time - 200/300/450 ns (max) • Totally static operation • Completely TTL compatible • 28 pin JEDEC approved pinout • UM23128A- automatic power down (CE) output enab |
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UMC |
16K x 8 NMOS ROM • EPROM pin compatible • 16,384 x 8 bit organization • single +5 volt supply • Access time - 200/300/450 ns (max) • Totally static operation • Completely TTL compatible • 28 pin JEDEC approved pinout • UM23128A- automatic power down (CE) output enab |
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UMC |
4K x 8 NMOS ROM • Access time 250/350/450ns (max.) • Single +5V ±10% power supply • TT L compatible inputs and outputs • Three-state outputs • Pin compatible with 2532 EPROM • Two programmable chip selects for output control • N-channel silicon gate technology Gen |
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UMC |
8K x 8 NMOS ROM • 2765 EPROM pin compatible • 8192 x 8 bit organization • Single + 5 volt supply • Access time - 200/300/450 ns (max) • Totally static operation • Completely TT L compatible • 28 Pin JEDEC approved pinout • UM2366A automatic power down (CE) output |
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UMC |
CMOS Mask Programmable ROM |
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UMC |
Dual Asynchronous Receiver/Transmitter • Dual full-duplex asynchronous receiver/transmitter • Ouadruple buffered receiver data registers • Programmable data format 5 to 8 data bits plus parity Odd, even, no parity or force parity 1, 1.5 or 2 stop bits programmable in 1/16 bit increments' |
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UMC |
Dual Asynchronous Receiver/Transmitter • Dual full-duplex asynchronous receiver/transmitter • Ouadruple buffered receiver data registers • Programmable data format 5 to 8 data bits plus parity Odd, even, no parity or force parity 1, 1.5 or 2 stop bits programmable in 1/16 bit increments' |
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UMC |
Enhanced Programmable Communications Interface |
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UMC |
32K x 8 NMOS ROM • EPROM pin compatible • 32,768 x 8 bit organization • Single +5 volt supply • Access time-200/300/450ns (max) • Totally static operation • Completely TTL compatible • 28 Pin JEDEC approved pinout • UM23256A- automatic power down (CE) output enable |
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UMC |
32K x 8 NMOS ROM • EPROM pin compatible • 32,768 x 8 bit organization • Single +5 volt supply • Access time-200/300/450ns (max) • Totally static operation • Completely TTL compatible • 28 Pin JEDEC approved pinout • UM23256A- automatic power down (CE) output enable |
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UMC |
8K x 8 NMOS ROM • 8192 x 8 Bit organization • Single +5 Volt Supply • Access Time - 200/300/450 ns (max.) • Totally static operation • Completely TT L compatible • 24 Pin JEDEC approved pinout General Description The UM2364 and UM2364A high performance Read Only Mem |
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UMC |
8K x 8 NMOS ROM • 8192 x 8 Bit organization • Single +5 Volt Supply • Access Time - 200/300/450 ns (max.) • Totally static operation • Completely TT L compatible • 24 Pin JEDEC approved pinout General Description The UM2364 and UM2364A high performance Read Only Mem |
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UMC |
8K x 8 NMOS ROM • 2765 EPROM pin compatible • 8192 x 8 bit organization • Single + 5 volt supply • Access time - 200/300/450 ns (max) • Totally static operation • Completely TT L compatible • 28 Pin JEDEC approved pinout • UM2366A automatic power down (CE) output |
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UMC |
4K x 8 NMOS ROM • Access time 250/350/450ns (max.) • Single +5V ±1 0% power supply • TT L compatible inputs and outputs • Three-state outputs • Pin compatible with 2732 EPROM • Two programmable chip selects for output control • N-channel silicon gate technology Ge |
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UMC |
Dual Asynchronous Receiver/Transmitter • Dual full-duplex asynchronous receiver/transmitter • Ouadruple buffered receiver data registers • Programmable data format 5 to 8 data bits plus parity Odd, even, no parity or force parity 1, 1.5 or 2 stop bits programmable in 1/16 bit increments' |
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UMC |
Dual Asynchronous Receiver/Transmitter • Dual full-duplex asynchronous receiver/transmitter • Ouadruple buffered receiver data registers • Programmable data format 5 to 8 data bits plus parity Odd, even, no parity or force parity 1, 1.5 or 2 stop bits programmable in 1/16 bit increments' |
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UMC |
CMOS Mask Programmable ROM |
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