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Toshiba Semiconductor |
8-Bit Shift Register/Latch • High speed: fmax = 55 MHz (typ.) at VCC = 5 V • Low power dissipation: ICC = 4 μA (max) at Ta = 25°C • High noise immunity: VNIH = VNIL = 28% VCC (min) • Output drive capability: 15 LSTTL loads for QA to QH 10 LSTTL loads for QH’ • Symmetrical outp |
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Toshiba |
Dual BCD Programmable Down Counter • High speed: fmax 40 MHz (typ.) at VCC = 5 V • Low power dissipation: ICC = 4 μA (max) at Ta = 25°C • High noise immunity: VNIH = VNIL = 28% VCC (min) • Output drive capability: 10 LSTTL loads • Symmetrical output impedance: |IOH| = IOL = 4 mA (min) |
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Toshiba |
2-Input AND Gate (1) AEC-Q100 (Rev. H) (Note 1) (2) Wide operating temperature range: Topr = -40 to 125 (Note 2) (3) High output current: ±24 mA (min) at VCC = 3.0 V (4) Super high speed operation: tpd = 2.4 ns (typ.) at VCC = 5.0 V, CL = 50 pF (5) Operation voltag |
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Toshiba Semiconductor |
Quad 2-Input NAND Gate • High speed: tpd = 6 ns (typ.) at VCC = 5 V • Low power dissipation: ICC = 1 μA (max) at Ta = 25°C • High noise immunity: VNIH = VNIL = 28% VCC (min) • Output drive capability: 10 LSTTL loads • Symmetrical output impedance: |IOH| = IOL = 4 mA (min) |
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Toshiba |
Octal D-Type Flip-Flop High speed: fmax = 185 MHz (typ.) at VCC = 5 V Low power dissipation: ICC = 4 µA (max) at Ta = 25°C High noise immunity: VNIH = VNIL = 28% VCC (min) Power down protection is provided on all inputs. Balanced propagation delays: tpLH ∼− tpHL |
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Toshiba |
Dual BUS Buffer • High speed: tpd = 10 ns (typ.) at VCC = 5 V • Low power dissipation: ICC = 2 µA (max) at Ta = 25°C • High noise immunity: VNIH = VNIL = 28% VCC (min) • Output drive capability: 15 LSTTL loads • Symmetrical output impedance: |IOH| = IOL = 6 mA (min) |
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Toshiba Semiconductor |
Quad 2-Input NAND Gate • High speed: tpd = 6 ns (typ.) at VCC = 5 V • Low power dissipation: ICC = 1 μA (max) at Ta = 25°C • High noise immunity: VNIH = VNIL = 28% VCC (min) • Output drive capability: 10 LSTTL loads • Symmetrical output impedance: |IOH| = IOL = 4 mA (min) |
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Toshiba |
2-INPUT AND GATE • High speed operation : tpd = 4.3ns (typ.) at VCC = 5V, 15pF • Low power dissipation : ICC = 2 μA (max) at Ta = 25°C • High noise immunity : VNIH = VNIL = 28% VCC (min) • 5.5-V tolerant inputs • Wide operating voltage range : VCC = 2 to 5.5 V TC7SH |
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Toshiba |
Dual Bilateral Switch • High speed: tpd = 7 ns (typ.) at VCC = 5 V • Low power dissipation: ICC = 1 μA (max) at Ta = 25°C • High noise immunity: VNIH = VNIL = 28% VCC (min) • Low ON resistance: RON = 50 Ω (typ.) at VCC = 9 V • High degree of linearity: THD = 0.05% (typ.) |
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Toshiba |
Hex D-Type Flip-Flop • High speed: fmax = 71 MHz (typ.) at VCC = 5 V • Low power dissipation: ICC = 4 μA (max) at Ta = 25°C • High noise immunity: VNIH = VNIL = 28% VCC (min) • Symmetrical output impedance: |IOH| = IOL = 4 mA (min) • Balanced propagation delays: tpLH ∼− |
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Toshiba |
SYNCHRONOUS UP/DOWN BINARY COUNTER • High speed: fmax = 54 MHz (typ.) at VCC = 5 V • Low power dissipation: ICC = 4 μA (max) at Ta = 25°C • High noise immunity: VNIH = |
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Toshiba Semiconductor |
Hex Inverter • High speed: tpd = 6 ns (typ.) at VCC = 5 V • Low power dissipation: ICC = 1 μA (max) at Ta = 25°C • High noise immunity: VNIH = VNIL = 28% VCC (min) • Output drive capability: 10 LSTTL loads • Symmetrical output impedance: |IOH| = IOL = 4 mA (min) |
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Toshiba Semiconductor |
Dual Bus Switch • • • • • • Operating voltage: VCC = 4.5~5.5 V High speed operation: tpd = 0.25 ns (max) Ultra-low on resistance: RON = 5 Ω (typ.) Electro-static discharge (ESD) performance: ±200 V or more (JEITA) ±2000 V or more (MIL) TTL level input (control input |
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Toshiba |
Octal Bus Transceiver (Note 1) (Note 2) (Note 3) High speed: tpd = 4.0 ns (typ.) at VCC = 5 V Low power dissipation: ICC = 4 µA (max) at Ta = 25°C High noise immunity: VNIH = VNIL = 28% VCC (min) Balanced propagation delays: tpLH ∼− tpHL Wide operating voltage |
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Toshiba |
System Power S-UFBGA45-0403-0.40-001 Weight: 10 mg (Typ.) Power supply voltage (VIN):2.9 V to 5.5 V (PVIN1 to 6):2.9 V to 5.5 V (LDO1_IN): 2.9 V to 5.5 V IC operation condition setting when the power supply voltage is set to 3.3 V/5.0 V by MODE_SEL pin. 6 |
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Toshiba |
Dual Comparator Low supply current: IDD = 20μA (typ.) Single power supply operation Wide common mode input voltage range: VSS to VDD−0.9V Push-pull output circuit Low input bias current Small package Weight SSOP8-P-0.65 : 0.021g (typ.) SSOP8-P-0.50A : 0 |
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Toshiba |
Dual BUS Buffer • High speed: tpd = 10 ns (typ.) at VCC = 5 V • Low power dissipation: ICC = 2 µA (max) at Ta = 25°C • High noise immunity: VNIH = VNIL = 28% VCC (min) • Output drive capability: 15 LSTTL loads • Symmetrical output impedance: |IOH| = IOL = 6 mA (min) |
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Toshiba |
Quad Exclusive OR Gate • High speed: tpd = 10 ns (typ.) at VCC = 5 V • Low power dissipation: ICC = 1 μA (max) at Ta = 25°C • High noise immunity: VNIH = VNIL = 28% VCC (min) • Output drive capability: 10 LSTTL loads • Symmetrical output impedance: |IOH| = IOL = 4 mA (min) |
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Toshiba |
Dual SPST Bus Switch (1) Operating voltage: VCC = 1.65 to 5.5 V (2) ON capacitance: CI/O = 10 pF Switch On (typ.) @VCC = 5.0 V (3) ON resistance: RON = 4 Ω (typ.) @VCC = 4.5 V, VIS = 0 V (4) ESD performance: Machine model ≥ ±200 V, Human body model ≥ ±2000 V (5) Package: |
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Toshiba |
3-TO-8 LINE DECODER • High speed: tpd = 5.5 ns (typ.) at VCC = 5 V • Low power dissipation: ICC = 4 μA (max) at Ta = 25°C • High noise immunity: VNIH = VNIL = 28% VCC (min) • Power down protection is provided on all inputs. • Balanced propagation delays: tpLH ∼− tpHL • |
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Desde 2024. D4U Semiconductor.
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