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System Logic Semiconductor |
Dual 2-Bit Transparent Latch = latched data SLS System Logic Semiconductor SL74HC75 MAXIMUM RATINGS * Symbol VCC VIN VOUT IIN IOUT ICC PD Tstg TL * Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC |
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System Logic Semiconductor |
Phase-Locked Loop egree phase shift between SIGIN and SL74HC4046D SOIC COMPIN signals (duty cycle is immaterial). The linear VCO produces an TA = -55° to 125° C for all packages output signal VCOOUT whose frequency is determined by the voltage of input VCOIN signal an |
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System Logic Semiconductor |
Octal 3-State Noninverting Transparent Latch(High-Performance Silicon-Gate CMOS) N VOUT IIN IOUT ICC PD Tstg TL * Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Current, per Pin DC Supply Current, VCC and GND Pins Powe |
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System Logic Semiconductor |
Quad 3-State Noninverting Buffers enced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Storage Tempe |
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System Logic Semiconductor |
Dual 4-Input Data Selector/Multiplexer L * Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, P |
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System Logic Semiconductor |
Octal 3-State Noninverting Buffer/Line Driver/Line Receiver MAXIMUM RATINGS * Symbol VCC VIN VOUT IIN IOUT ICC PD Tstg TL * Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Current, per Pin DC Supply |
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System Logic Semiconductor |
Octal 3-State Noninverting Bus Transceiver ata Transmitted from Bus A to Bus B Buses Isolated (High Impedance State) L H H X X = don’t care SLS System Logic Semiconductor SL74LS245 MAXIMUM RATINGS * Symbol VCC VIN VOUT Tstg * Parameter Supply Voltage Input Voltage Output Voltage Stor |
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System Logic Semiconductor |
Quad 2-Input Exclusive OR Gate 70 Max 5.25 Unit V V V mA mA °C DC ELECTRICAL CHARACTERISTICS over full operating conditions Guaranteed Limit Symbol VIK VOH VOL Parameter Input Clamp Voltage High Level Output Voltage Low Level Output Voltage Test Conditions VCC = min, IIN = -18 mA |
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System Logic Semiconductor |
Hex Inverter with Open-Drain Outputs OUT IIN IOUT ICC PD Tstg TL * Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power D |
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System Logic Semiconductor |
Octal 3-State Bus Transceivers nable. In this configuration each output reinforces its input. Thus, when all other data sources to the two sets of bus lines are at high impedance, each set of bus lines will remain at its last state. The SL74HC651 has inverted outputs. • Outputs Di |
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System Logic Semiconductor |
Quad 2-Input OR Gate(High-Performance Silicon-Gate CMOS) Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) Value -0.5 to +7.0 -1.5 to VCC +1.5 -0.5 to VCC +0.5 ±20 ±25 ±50 750 500 -65 to +150 260 Unit V V V mA mA mA mW °C °C Maximum Ratings are those values beyond which damage to |
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System Logic Semiconductor |
Quad 2-Input Data Selector/Multiplexer 0 Unit V V V °C Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. RECOMMENDED OPERATING CONDITIONS Symbol VCC VIH VIL IOH IOL TA Supply |
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System Logic Semiconductor |
Dual J-K Flip-Flop with Set and Reset ble if Set and Reset go high simultaneously X = Don’t Care SLS System Logic Semiconductor SL74HC112 MAXIMUM RATINGS * Symbol VCC VIN VOUT IIN IOUT ICC PD Tstg TL * Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to G |
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System Logic Semiconductor |
Octal 3-State Noninverting Bus Transceiver us B to Bus A Data Transmitted from Bus A to Bus B Buses Isolated (High Impedance State) L H H X X = don’t care SLS System Logic Semiconductor SL74HC245 MAXIMUM RATINGS * Symbol VCC VIN VOUT IIN IOUT ICC PD Tstg TL * Parameter DC Supply Vol |
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System Logic Semiconductor |
Hex Inverters with Open-Drain Outputs t V V V °C Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. RECOMMENDED OPERATING CONDITIONS Symbol VCC VIH VIL VOH IOL TA Supply Voltag |
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System Logic Semiconductor |
3-to-8-Line Decoder/Demultiplexer X X H H H H H H H H L L L L L L L L L L L L L L L L A2 A1 A0 X X X X X X X X X L L L L L H L H L L H H H L L H L H H H L H H H Outputs Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 H H H H H H H H H H H H H H H H H H H H H H H H L H H H H H H H H L H H H H H H H H L H H H |
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System Logic Semiconductor |
Synchronous 4 Bit Counters; Binary/ Direct Reset an internal carry look-ahead for application in high-speed counting designs. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change conicident with each other when so instructed by the count-enabl |
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System Logic Semiconductor |
8-Bit Serial-Input/Parallel-Output Shift Register gated serial inputs and an asynchronous reset. The gated serial inputs (A and B) permit complete control over incoming data as a low at either (or both) input(s) inhibits entry of the new data and resets the first flip flop to the low level at the ne |
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System Logic Semiconductor |
Hex Inverter m Case for 10 seconds (Plastic DIP ), 0.3 mm (SOIC Package) Value -0.5 ~ +7.0 ±20 ±50 ±25 ±50 ±50 750 500 -65 ~ +150 260 Unit V mA mA mA mA mA mW °C °C IOK* 2 Io* 3 IGND ICC PD Tstg TL * Maximum Ratings are those values beyond which damage to th |
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System Logic Semiconductor |
Hex Schmitt-Trigger Inverter package+ Storage temperature Lead temperature, 1.5 mm from Case for 10 seconds (Plastic DIP ), 0.3 mm (SOIC Package) Value -0.5 ~ +7.0 ±20 ±50 ±25 ±50 ±50 750 500 -65 ~ +150 260 Unit V mA mA mA mA mA mW °C °C IGND ICC PD Tstg TL * Maximum Rating |
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Desde 2024. D4U Semiconductor.
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