| No. | parte # | Fabricante | Descripción | Hoja de Datos |
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Siemens |
8/16 Kbit (1024/2048 x 8 bit) Serial CMOS-EEPROM • Data EEPROM internally organized as 1024/2048 bytes and 64/128 pages × 16 bytes • Low power CMOS • VCC = 2.7 to 5.5 V operation • Two wire serial interface bus, I2C-Bus compatible • Filtered inputs for noise suppression with Schmitt trigger • Clock |
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Siemens |
32 Kbit (4096 x 8 bit) Serial CMOS-EEPROM • Data EEPROM internally organized as 4096 bytes and 128 pages × 32 bytes • Page Protection Mode for protecting the EEPROM against unintended data changes (SLx 24C32.../P types only) • Low power CMOS • VCC = 2.7 to 5.5 V operation • Two wire serial i |
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Siemens Semiconductor Group |
(SLE44xx) ICs for Chip Cards • • • • • • • • • • • • • • SLE 4432 SLE 4442 www.DataSheet4U.com 256 x 8-bit EEPROM organization Byte-wise addressing Irreversible byte-wise protection of lowest 32 addresses (Byte 0...31) 32 x 1-bit organization of protection memory Two-wire lin |
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Siemens Semiconductor Group |
(SLE44xx) ICs for Chip Cards • • • • • • • • • • • • • • SLE 4432 SLE 4442 www.DataSheet4U.com 256 x 8-bit EEPROM organization Byte-wise addressing Irreversible byte-wise protection of lowest 32 addresses (Byte 0...31) 32 x 1-bit organization of protection memory Two-wire lin |
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Siemens |
Standard EEPROM |
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Siemens Semiconductor Group |
(SLE44xx) ICs for Chip Cards • • • • • • • • • • • • • • SLE 4432 SLE 4442 www.DataSheet4U.com 256 x 8-bit EEPROM organization Byte-wise addressing Irreversible byte-wise protection of lowest 32 addresses (Byte 0...31) 32 x 1-bit organization of protection memory Two-wire lin |
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Siemens Semiconductor Group |
(SLE4418 / SLE4428) ICs for Chip Cards www.DataSheet4U.com q q q q q q q q q 1024 x 8 bit EEPROM organization Byte-wise addressing Irreversible byte-wise write protection 1024 x 1 bit protection memory organization Serial three-wire bus End of programming indicated on data output Minimu |
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Siemens Semiconductor Group |
(SLE4418 / SLE4428) ICs for Chip Cards www.DataSheet4U.com q q q q q q q q q 1024 x 8 bit EEPROM organization Byte-wise addressing Irreversible byte-wise write protection 1024 x 1 bit protection memory organization Serial three-wire bus End of programming indicated on data output Minimu |
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Siemens |
Standard EEPROM |
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Siemens |
4 Kbit (512 x 8 bit) Serial CMOS-EEPROM • Data EEPROM internally organized as 512 bytes and 32 pages × 16 bytes • Low power CMOS • VCC = 2.7 to 5.5 V operation • Two wire serial interface bus, I2C-Bus compatible • Filtered inputs for noise suppression with Schmitt trigger • Clock frequency |
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Siemens |
(SLE4432 / SLE4442) 256 Byte EEPROM q 256 × 8-bit EEPROM organization q Byte-wise addressing q Irreversible byte-wise write protection of lowest q q q q q q q q 32 addresses (Byte 0 ... 31) 32 × 1-bit organization of protection memory Two-wire link protocol End of processing indicated |
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Siemens Semiconductor Group |
(SLE44xx) ICs for Chip Cards • • • • • • • • • • • • • • SLE 4432 SLE 4442 www.DataSheet4U.com 256 x 8-bit EEPROM organization Byte-wise addressing Irreversible byte-wise protection of lowest 32 addresses (Byte 0...31) 32 x 1-bit organization of protection memory Two-wire lin |
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Siemens |
Standard EEPROM |
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Siemens |
16 Kbit (2048 x 8 bit) Serial CMOS-EEPROM • Data EEPROM internally organized as 2048 bytes and 128 pages × 16 bytes • Low power CMOS • VCC = 2.7 to 5.5 V operation • Two wire serial interface bus, I2C-Bus compatible • Three chip select pins to address 8 devices • Filtered inputs for noise su |
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Siemens |
8/16 Kbit (1024/2048 x 8 bit) Serial CMOS-EEPROM • Data EEPROM internally organized as 1024/2048 bytes and 64/128 pages × 16 bytes • Low power CMOS • VCC = 2.7 to 5.5 V operation • Two wire serial interface bus, I2C-Bus compatible • Filtered inputs for noise suppression with Schmitt trigger • Clock |
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Siemens |
(SLE4432 / SLE4442) 256 Byte EEPROM q 256 × 8-bit EEPROM organization q Byte-wise addressing q Irreversible byte-wise write protection of lowest q q q q q q q q 32 addresses (Byte 0 ... 31) 32 × 1-bit organization of protection memory Two-wire link protocol End of processing indicated |
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Desde 2024. D4U Semiconductor.
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