| No. | parte # | Fabricante | Descripción | Hoja de Datos |
|---|---|---|---|---|
|
|
|
Sanyo |
8-Bit Single Chip Microcontroller (1) Read-Only Memory (ROM) - 73728 × 8 bits (LC877372A) - 65536 × 8 bits (LC877364A) - 57344 × 8 bits (LC877356A) - 49152 × 8 bits (LC877348A) (2) Random Access Memory (RAM): 2048 × 9 bits (LC877372A, LC877364A, LC877356A, LC877348A) (3) Minimum Bu |
|
|
|
|
Sanyo Semicon Device |
Single-Chip Facsimile Controller , 7.2, 4.8, and 3.6 kHz – RTC low-voltage backup – 5-V single-voltage power supply Functions • CPU and peripheral circuits – High-speed 16-bit CPU (65C816) operating at 7.4 MHz – 16-MB program address space – CODEC accelerator – Two-channel DMA cont |
|
|
|
|
Sanyo Semicon Device |
8-bit 1-chip Microcontroller such as 8K-byte flash ROM (On-boardprogrammable), 256-byte RAM, an On-chip-debugger, sophisticated 16-bit timers/counters (may be divided into 8-bit timers), a 16-bit timer/counter (may be divided into 8-bit timers/counters or 8-bit PWMs), two 8-bit |
|
|
|
|
Sanyo Semicon Device |
8-Bit Single Chip Microcontroller (1) Read-Only Memory (ROM) : 32768 × 8 bits / 28672 × 8 bits / 24576 × 8 bits 20480 × 8 bits / 16384 × 8 bits for program 16128 × 8 bits for CGROM 512 × 8 bits (including 128 bytes for ROM correction function) 352 × 9 bits (for CRT display) (2) Rand |
|
|
|
|
Sanyo |
PAL CCD 1H Delay Line |
|
|
|
|
Sanyo Semicon Device |
Image Data Compression/Expansion Processor • Conforms to the ITU-T T.4 and T.6 MH, MR, and MMR encoding methods. • Supports G3 and G4 facsimile. • Handles up to 64k bits in the main scan direction. • Line skip mode • 8/16-bit image memory bus, 8-bit CPU bus • Supports data transfers between t |
|
|
|
|
Sanyo |
8-bit 1-chip Microcontroller such as 128K/112K-byte ROM, 4K-byte RAM, two sophisticated 16-bit timers/counters (may be divided into 8-bit timers), four 8-bit timers with a prescaler, a base timer serving as a time-of-day clock, two synchronous SIO ports (with automatic block tra |
|
|
|
|
Sanyo |
8-Bit Single Chip Microcontroller (1) Read-Only Memory (ROM) : LC866448B 49152 × 8 bits : LC866444B 45056 × 8 bits : LC866440B 40960 × 8 bits : LC866436B 36864 × 8 bits : LC866432B 32768 × 8 bits : LC866428B 28672 × 8 bits : LC866424B 24576 × 8 bits : LC866420B 20480 × 8 bits : LC866 |
|
|
|
|
Sanyo |
8-Bit Single Chip Microcontroller with the UVEPROM (1) Read Only Memory (ROM) : LC866548A : LC866540A : LC866532A : LC866528A : LC866524A 49152 × 8 bits 40960 × 8 bits 32768 × 8 bits 28672 × 8 bits 24576 × 8 bits Ver.1.05 71896 91400 RM (IM) SK No.6700-1/21 LC866548/40/32/28/24A (2) Random Access |
|
|
|
|
Sanyo |
8-Bit Single Chip Microcontroller (1) Option switching by PROM data The option function of the LC865400 series can be specified by the PROM data. The LC86P5420 can be checked the functions of the trial pieces using the mass production board. (2) Internal one-time PROM capacity : 2073 |
|
|
|
|
Sanyo |
8-Bit Single-Chip Microcontroller (1) Read-Only Memory (ROM): LC876694B LC876678B LC876662B 98304 × 8 bits 81920 × 8 bits 65536 × 8 bits (2) Random Access Memory (RAM): LC876694B/78B/62B 2048 × 9 bits (3) Minimum Bus Cycle Time: 100ns (10MHz) Note: The bus cycle time indicates ROM r |
|
|
|
|
Sanyo |
Digital Audio Interface Receiver • On-chip PLL circuit synchronizes with the transmitted IEC 958 and EIAJ CP-1201 format signal. • Provides 128fs, bit, and L/R clock outputs. • System clock can be selected to be either 384fs or 512fs. • Microprocessor interface code settings for dif |
|
|
|
|
Sanyo |
CD-ROM/CD-I Error Correction/ Host Interface LSI • Software and pin compatibility with the LC8951 (Changes were made to internal registers, the SRAM interface, and other aspects.) • Support for CD-ROM (mode 1) and CD-I (mode 2, forms 1 and 2) • All CD-ROM/CD-I special functions implemented on a sin |
|
|
|
|
Sanyo |
NTSC Format Delay Line • Requires only the input of a 3.58-MHz clock to produce a 1H delayed signal and the external low-pass filter. • Uses a 5-V single-voltage power supply. • Requires a minimal number of external components due to the peripheral components provided on c |
|
|
|
|
Sanyo |
PAL CCD Delay Line |
|
|
|
|
Sanyo Electric |
(LC876964C/56C/48C) 8-Bit Single Chip Microcontroller (1) Read-Only Memory (ROM): LC876964C LC876956C LC876948C 65536 × 8bits 57344 × 8bits 49152 × 8bits (LC876980B/72B/64B) (2) Random Access Memory (RAM): 2048 × 9 bits (3) Minimum Bus Cycle Time: 100ns (10MHz) VDD=3.0 ～ 5.5[V] 250ns (4MHz) VDD=2.5 ～ |
|
|
|
|
Sanyo Electric |
(LC876772B/80B86B) 8_bit Signal Chup Microcontroller (1) Read-Only Memory (ROM): LC876796B 98304 × 8 bits : LC876780B 81920 × 8 bits : LC876772B 73728 × 8 bits (2) Random Access Memory (RAM): LC876796B/80B/72B (3) Minimum Bus Cycle Time: 100ns (10MHz) Note: The bus cycle time indicates ROM read time. ( |
|
|
|
|
Sanyo Semicon Device |
LC89170M • Accepts the channel R to W subcode data through a subcode interface. • Can continuously output the channel R to W data for each 1PACK24 symbol. • Performs error detection (cyclic redundancy code) and outputs both the data and the result of that che |
|
|
|
|
Sanyo Semicon Device |
Image-Processing LSI • Number of pixels processed: 2040 pixels/line • Processing speed: 500 ns/pixel maximum (when the CLKIN input frequency is 32 MHz) • Built-in 8-bit A/D converter (includes a sensor signal delay adjustment function) • Built-in 6-bit D/A converter for |
|
|
|
|
Sanyo Semicon Device |
Image-Processing LSI • Number of pixels processed: 2040 pixels/line • Processing speed: 500 ns/pixel maximum (when the CLKIN input frequency is 32 MHz) • Built-in 8-bit A/D converter (includes a sensor signal delay adjustment function) • Built-in 6-bit D/A converter for |
|
Desde 2024. D4U Semiconductor.
|