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SamHop |
Dual N-Channel Enhancement Mode Field Effect Transistor Super high dense cell design for low RDS(ON). Rugged and reliable. Wafer level CSP. ESD Protected. WLCSP TOP VIEW BOTTOM VIEW 1.77 4x 0.25 0.03 3.54 8611S Date Code 1.25 0.03 43 52 61 Mark area 1-pin index mark S1 3 2x φ 0.25 0.03 2 1 0.10 |
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SamHop |
Dual N-Channel Enhancement Mode Field Effect Transistor Super high dense cell design for low RDS(ON). Rugged and reliable. Wafer level CSP. ESD Protected. WLCSP TOP VIEW 1.61 0.03 BOTTOM VIEW 0.65 LAND PATTERN (REFERENCE) 0.65 2.55 0.03 8100S Date Code S1 S2 G1 G2 S1 S2 0.65 0.65 0.65 0.65 1-pi |
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SamHop |
Dual N-Channel Enhancement Mode Field Effect Transistor Super high dense cell design for low RDS(ON). Rugged and reliable. Wafer level CSP. ESD Protected. WLCSP TOP VIEW 1.98 0.02 8273 Date Code 1.98 0.02 BOTTOM VIEW 0.65 G2 S2 G1 S1 0.65 1-pin index mark S1 Mark area 0.13 0.01 4 - φ 0.28 S1: |
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SamHop |
Dual N-Channel Enhancement Mode Field Effect Transistor Super high dense cell design for low RDS(ON). Rugged and reliable. Wafer level CSP. ESD Protected. WLCSP index mark S2 TOP VIEW 1.98 0.02 BOTTOM VIEW 0.66 0.65 3.20 0.02 8380 Date Code 5 4 3 2 Mark area 6 7 8 1 0.61 S1 S2 S1 S2 S1 S2 G1 G2 |
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SamHop |
Dual N-Channel Enhancement Mode Field Effect Transistor Super high dense cell design for low RDS(ON). Rugged and reliable. Wafer level CSP. ESD Protected. WLCSP TOP VIEW BOTTOM VIEW 1.57 0.03 4x 0.25 0.03 3.54 0.03 8605S Date Code 1.25 0.03 43 52 61 Mark area 1-pin index mark S1 3 2x φ 0.25 0.03 |
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SamHop |
Dual N-Channel Enhancement Mode Field Effect Transistor Super high dense cell design for low RDS(ON). Rugged and reliable. Wafer level CSP. ESD Protected. WLCSP TOP VIEW BOTTOM VIEW 1.57 0.03 4x 0.25 0.03 3.54 0.03 8604 Date Code 1.25 0.03 43 52 61 Mark area 1-pin index mark S1 3 2x φ 0.25 0.03 |
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SamHop |
Dual N-Channel Enhancement Mode Field Effect Transistor Super high dense cell design for low RDS(ON). Rugged and reliable. Wafer level CSP. ESD Protected. WLCSP TOP VIEW 1.75 0.03 8220 Date Code 1.75 0.03 BOTTOM VIEW 0.65 G2 S2 G1 S1 0.65 1-pin index mark S1 Mark area 0.210 0.010 0.107 0.007 |
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SamHop |
Dual N-Channel Enhancement Mode Field Effect Transistor Super high dense cell design for low RDS(ON). Rugged and reliable. Wafer level CSP. ESD Protected. WLCSP TOP VIEW 1.61 0.03 BOTTOM VIEW 0.65 LAND PATTERN (REFERENCE) 0.65 2.55 0.03 8260 Date Code Mark area 1-pin index mark S1 0.16 0.01 S1 S |
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SamHop |
Dual N-Channel Enhancement Mode Field Effect Transistor Super high dense cell design for low RDS(ON). Rugged and reliable. Wafer level CSP. ESD Protected. WLCSP TOP VIEW 1.77 0.04 BOTTOM VIEW 0.485 0.80 LAND PATTERN (REFERENCE) 0.80 43 3.05 0.04 8650 Date Code 1.005 1.005 0.8775 0.8775 0.6475 0.8 |
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SamHop |
Dual N-Channel Enhancement Mode Field Effect Transistor Super high dense cell design for low RDS(ON). Rugged and reliable. Wafer level CSP. ESD Protected. WLCSP TOP VIEW 1.88 0.03 8180S Date Code 1.88 0.03 BOTTOM VIEW 0.65 G2 S2 G1 S1 0.65 1-pin index mark S1 Mark area 0.100 0.010 4 - φ 0.31 |
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SamHop |
Dual N-Channel Enhancement Mode Field Effect Transistor Super high dense cell design for low RDS(ON). Rugged and reliable. Wafer level CSP. ESD Protected. 1.54 0.03 WLCSP TOP VIEW 1.54 0.03 8200 Date Code BOTTOM VIEW 0.65 G2 S2 G1 S1 0.65 1-pin index mark S1 Mark area 0.210 0.010 0.107 0.007 |
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SamHop |
Dual N-Channel Enhancement Mode Field Effect Transistor Super high dense cell design for low RDS(ON). Rugged and reliable. Wafer level CSP. ESD Protected. BOTTOM VIEW 0.65 2.75 0.03 8232 Date Code Mark area 1-pin index mark S1 0.210 0.010 0.107 0.007 S1 S2 G1 G2 S1 S2 0.65 0.65 S1: Source 1 G1: Ga |
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SamHop |
Dual N-Channel Enhancement Mode Field Effect Transistor Super high dense cell design for low RDS(ON). Rugged and reliable. Wafer level CSP. ESD Protected. WLCSP TOP VIEW 1.98 0.02 8237 Date Code 1.98 0.02 BOTTOM VIEW 0.65 G2 S2 G1 S1 0.65 1-pin index mark S1 Mark area 0.20 0.01 4 - φ 0.31 S1: |
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SamHop |
Dual N-Channel Enhancement Mode Field Effect Transistor Super high dense cell design for low RDS(ON). Rugged and reliable. Wafer level CSP. ESD Protected. BOTTOM VIEW 0.65 1.98 0.02 8238 Date Code G2 S2 G1 S1 0.65 1-pin index mark S1 Mark area 0.13 0.01 S1 : Source 1 G1 : Gate 1 G2 : Gate 2 S2 : |
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SamHop |
Dual N-Channel Enhancement Mode Field Effect Transistor Super high dense cell design for low RDS(ON). Rugged and reliable. Wafer level CSP. ESD Protected. WLCSP TOP VIEW 1.55 0.05 3.45 0.05 8301 Date Code Mark area 1-pin index mark S1 0.21 BOTTOM VIEW 0.65 S1 S2 S1 S2 G1 G2 S1 S2 S1 S2 0.65 0.6 |
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SamHop |
Dual N-Channel Enhancement Mode Field Effect Transistor Super high dense cell design for low RDS(ON). Rugged and reliable. Wafer level CSP. ESD Protected. WLCSP TOP VIEW 1.77 0.04 BOTTOM VIEW 0.485 0.80 LAND PATTERN (REFERENCE) 0.80 43 3.05 0.04 8652S Date Code 1.005 1.005 0.8775 0.8775 0.6475 0. |
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SamHop |
Dual N-Channel Enhancement Mode Field Effect Transistor Super high dense cell design for low RDS(ON). Rugged and reliable. Wafer level CSP. ESD Protected. WLCSP TOP VIEW 1.33 0.03 8252B Date Code 1.33 0.03 BOTTOM VIEW 0.65 G2 S2 G1 S1 0.65 1-pin index mark S1 Mark area 0.210 0.010 0.107 0.007 |
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SamHop |
Dual N-Channel Enhancement Mode Field Effect Transistor Super high dense cell design for low RDS(ON). Rugged and reliable. Wafer level CSP. ESD Protected. WLCSP TOP VIEW BOTTOM VIEW 1.57 0.03 4x 0.25 0.03 3.54 0.03 8605 Date Code 1.25 0.03 43 52 61 Mark area 1-pin index mark S1 3 2x φ 0.25 0.03 |
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SamHop |
Dual N-Channel Enhancement Mode Field Effect Transistor Super high dense cell design for low RDS(ON). Rugged and reliable. Wafer level CSP. ESD Protected. WLCSP TOP VIEW BOTTOM VIEW 1.77 4x 0.25 0.03 3.54 8611 Date Code 1.25 0.03 43 52 61 Mark area 1-pin index mark S1 3 2x φ 0.25 0.03 2 1 0.16 |
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SamHop |
Dual N-Channel Enhancement Mode Field Effect Transistor Super high dense cell design for low RDS(ON). Rugged and reliable. Wafer level CSP. ESD Protected. WLCSP TOP VIEW 1.77 0.04 BOTTOM VIEW 0.485 0.80 LAND PATTERN (REFERENCE) 0.80 43 3.05 0.04 8652 Date Code 1.005 1.005 0.8775 0.8775 0.6475 0.8 |
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Desde 2024. D4U Semiconductor.
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