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ST Microelectronics |
8 BIT PISO SHIFT REGISTER M74HC166B1R M74HC166M1R T&R M74HC166RM13TR M74HC166TTR enabled and synchronous loading occurs on the next clock pulse. Clocking is accomplished on the low-to-high level edge of the clock pulse. The CLOCK-INHIBIT input should be changed to the high |
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ST Microelectronics |
TRIPLE 3-INPUT NAND GATE 8 7 14 SYMBOL 1A to 3A 1B to 3B 1C to 3C 1Y to 3Y GND VCC NAME AND FUNCTION Data Inputs Data Inputs Data Inputs Data Outputs Ground (0V) Positive Supply Voltage TRUTH TABLE A L X X H X : Don‘t Care B X L X H C X X L H Y H H H L ABSOLUTE MAXIMUM |
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ST Microelectronics |
SYNCHRONOUS UP/DOWN BINARY COUNTER allows the counters to be used as divide-by-n counters by modifying the count length with the preset inputs. In addition the counter can also be cleared. This is accomplished by inputting a high on the CLEAR input. All 4 internal stages are set to lo |
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ST Microelectronics |
4 BIT PIPO SHIFT REGISTER a system designer may want in a shift register. It features parallel inputs, parallel outputs, right shift and left shift serial inputs, clear line. The register has four distinct modes of operation : PARALLEL (broadside) LOAD ; SHIFT RIGHT (in the d |
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ST Microelectronics |
8 BIT PIPO SHIFT REGISTER parallel inputs, parallel outputs, J-K serial inputs, a SHIFT/LOAD control input, and a direct overriding CLEAR. This shift register can operate in two modes : Parallel Load ; Shift from QA towards QD. Parallel loading is accomplished by applying the |
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ST Microelectronics |
QUAD 2-INPUT NAND GATE 14 SYMBOL 1A to 4A 1B to 4B 1Y to 4Y GND VCC NAME AND FUNCTION Data Inputs Data Inputs Data Outputs Ground (0V) Positive Supply Voltage TRUTH TABLE A L L H H B L H L H Y H H H L ABSOLUTE MAXIMUM RATINGS Symbol VCC VI VO IIK IOK IO PD Tstg TL Suppl |
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ST Microelectronics |
SYNCHRONOUS PRESETTABLE 4-BIT COUNTER inary counters. The CLOCK input is active on the rising edge. Both LOAD and CLEAR inputs are active Low. Presetting of all four IC’s is synchronous on the rising edge of the CLOCK. The function on the M54/74HC162/163 is synchronous to CLOCK, while th |
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ST Microelectronics |
SYNCHRONOUS PRESETTABLE 4-BIT COUNTER inary counters. The CLOCK input is active on the rising edge. Both LOAD and CLEAR inputs are active Low. Presetting of all four IC’s is synchronous on the rising edge of the CLOCK. The function on the M54/74HC162/163 is synchronous to CLOCK, while th |
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ST Microelectronics |
8-bit PISO shift register d must be high. The two clock input perform identically; one can be used as a clock inhibit by applying a high signal; to permit this operation clocking is accomplished through a 2 input nor gate. To avoid double clocking, however, the inhibit signa |
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STMicroelectronics |
SYNCHRONOUS UP/DOWN DECADE COUNTER |
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ST Microelectronics |
OCTAL D-TYPE LATCH ght outputs will be in a normal logic state (high or low logic level) and while high level the outputs will be in a high impedance state. The 3-State output configuration and the wide choice of outline make bus organized system simple. All inputs are |
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ST Microelectronics |
DUAL J-K FLIP FLOP rge and transient excess voltage. Obsolete ProducPIN CONNECTION AND IEC LOGIC SYMBOLS August 2001 1/11 M74HC107 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL NAME AND FUNCTION 1, 8, 4, 11 1J, 2J, 1K, Synchronous Inputs; |
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ST Microelectronics |
TRIPLE 3-INPUT AND GATE 8 7 14 SYMBOL 1A to 3A 1B to 3B 1C to 3C 1Y to 3Y GND VCC NAME AND FUNCTION Data Inputs Data Inputs Data Inputs Data Outputs Ground (0V) Positive Supply Voltage TRUTH TABLE A L X X H X : Don’t Care B X L X H C X X L H Y L L L H ABSOLUTE MAXIMUM |
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ST Microelectronics |
DUAL J-K FLIP FLOP WITH PRESET he logic level of the J and K inputs may be allowed to change when the clock pulse is HIGH and the bistable will function as shown in the truth table as long as minimum set-up times are observed. Input data is transferred to the outputs on the negati |
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ST Microelectronics |
HEX SCHMITT INVERTER 1/8 M74HC14 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No 1, 3, 5, 9, 11, 13 2, 4, 6, 8, 10, 12 7 14 SYMBOL 1A to 6A 1Y to 6Y GND VCC NAME AND FUNCTION Data Inputs Data Outputs Ground (0V) Positive Supply Voltage TRUTH TABLE A L H Y H |
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ST Microelectronics |
8 BIT SIPO SHIFT REGISTER both true (Y) and complement (W) outputs as well as STROBE input. The STROBE must be a low logic level to enable this device. When the STROBE input is high, both outputs are in the high impedance state. When enabled, address information on the data s |
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ST Microelectronics |
QUAD 2 CHANNEL MULTIPLEXER osen. All inputs are equipped with protection circuits against static discharge and transient excess voltage. Obsolete ProduPIN CONNECTION AND IEC LOGIC SYMBOLS August 2001 1/11 M74HC257 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN |
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ST Microelectronics |
PROGRAMMABLE DIVIDER/TIMER an active-low clear input to initialize the state of all flip-flops. To facilitate incoming inspection, test points are provided. (TP1, TP2 and TP3 on the HC292/7292 and TP on the HC294/7294). All inputs are equipped with protection circuits against |
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STMicroelectronics |
M74HC4851 ■ Low power dissipation – ICC = 2 μA (max.) at TA = 25 °C ■ Injection current protection – VΔOUT < 1 mV at VCC = 5 V, IIN ≤ 1 mA – RS ≤ 3.9 kΩ ■ “ON” resistance at TA = 25 °C – 215 Ω typ. (VCC = 3.0 V) – 160 Ω typ. (VCC = 4.5 V) – 150 Ω typ. (VCC = 6 |
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STMicroelectronics |
HEX D-TYPE FLIP FLOP y 2001 1/11 M74HC174 INPUT AND OUTPUT EQUIVALENT CIRCUIT TRUTH TABLE INPUTS CLEAR D CK L X X H L H H H X X : Don’t Care LOGIC DIAGRAM PIN DESCRIPTION PIN No 1 2, 5, 7, 10, 12, 15 3, 4, 6, 11, 13, 14 9 8 16 SYMBOL CLEAR NAME AND |
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Desde 2024. D4U Semiconductor.
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