Renesas CS8 Hoja de datos

No.	parte #	Fabricante	Descripción
1	ICS8516I	Renesas	Clock Distribution • Sixteen Differential LVDS outputs • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • Maximum output frequency: 700MHz • Translates any differential input signal (LVPECL, LVHSTL, SSTL, DCM) to LVD
2	ICS853S310I	Renesas	3.3V LVPECL/ECL Fanout Buffer • Eight differential 3.3V LVPECL/ECL outputs • Two selectable differential input pairs • PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML, SSTL • Maximum output frequency: 2GHz • Translates any single-ended in
3	ICS84330-02	Renesas	Crystal-to-3.3V Differential LVPECL Frequency Synthesizer The 84330-02 is a general purpose, single output high frequency synthesizer. The VCO operates at a frequency range of 250MHz to 700MHz. The VCO and output frequency can be programmed using the serial or parallel interfaces to the configuration logic
4	ICS8305I-02	Renesas	LVCMOS-to-LVCMOS Fanout Buffer • Four LVCMOS/LVTTL outputs, (two banks of two LVCMOS outputs) • Selectable differential CLK, nCLK pair or LVCMOS_CLK input • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL • LVCMOS_CLK supports the foll
5	ICS851S201I	Renesas	Differential-to-HCSL Multiplexer • Two differential HCSL output pairs • Two selectable differential clock input pairs • CLKx, nCLKx pairs can accept HCSL level inputs • Low level input detection on selected input (latched) • Maximum Input frequency: 250MHz • Output skew: 5ps (typica
6	ICS84330CI	Renesas	Crystal-to-LVPECL Frequency Synthesizer • Fully integrated PLL, no external loop filter requirements • One differential 3.3V LVPECL output • Crystal oscillator interface: 10MHz to 25MHz • Output frequency range: 31.25MHz to 720MHz • VCO range: 250MHz to 720MHz • Parallel or serial interfac
7	ICS853S012I	Renesas	LVPECL Clock/Data Multiplexer • High speed 12:1 differential multiplexer • One differential 3.3V or 2.5V LVPECL output • Twelve selectable differential clock or data inputs • CLKx, nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML • Maximum output
8	ICS853S006I	Renesas	LVPECL/ECL Fanout Buffer • Six differential 2.5V, 3.3V LVPECL/ECL outputs • One differential PCLK, nPCLK input pair • PCLK, nPCLK pair can accept the following differential input levels: LVPECL, LVDS, CML • Maximum output frequency: 2GHz • Output skew: 50ps (max) • Part-to-p
9	ICS8543	Renesas	Differential-to-LVDS Fanout Buffer • Four differential LVDS output pairs • Selectable differential CLK, nCLK or LVPECL clock inputs • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • PCLK, nPCLK pair can accept the following differe
10	ICS84330C	Renesas	Single output high frequency synthesizer • Fully integrated PLL, no external loop filter requirements • One differential 3.3V LVPECL output • Crystal oscillator interface: 10MHz to 25MHz • Output frequency range: 31.25MHz to 700MHz • VCO range: 250MHz to 700MHz • Parallel or serial interfac
11	ICS8545-02	Renesas	1-TO-4 LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER • Four differential LVDS output pairs • Two LVCMOS/LVTTL clock inputs to support redundant or selectable frequency fanout applications • Maximum output frequency: 350MHz • Translates LVCMOS/LVTTL input signals to LVDS levels • Output skew: 60ps (maxi
12	ICS850S1601I	Renesas	SINGLE-ENDED MULTIPLEXER • 16:1 single-ended multiplexer • Nominal output impedance: 20Ω (VDD = 3.3V) • Maximum output frequency: 250MHz • Propagation delay: 2.7ns (maximum) • Full 3.3V or 2.5V supply modes • -40°C to 85°C ambient operating temperature • Available in lead-fr
13	ICS854S058I	Renesas	8:1 Differential-to-LVDS Clock Multiplexer • High speed 8:1 differential multiplexer • One differential LVDS output pair • Eight selectable differential PCLK, nPCLK input pairs • PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, SSTL, CML • Maximum output f
14	ICS854S054I	Renesas	4:1 Differential-to-LVDS Clock Multiplexer • High speed 4:1 differential multiplexer • One differential LVDS output pair • Four selectable differential PCLK, nPCLK input pairs • PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML • Maximum output frequenc
15	ICS854S01I	Renesas	2:1 Differential-to-LVDS Multiplexer • 2:1 LVDS MUX • One LVDS output pair • Two differential clock inputs can accept: LVPECL, LVDS, CML • Maximum input/output frequency: 2.5GHz • Translates LVCMOS/LVTTL input signals to LVDS levels by using a resistor bias network on nPCLK0, nPCLK1 • R
16	ICS8543I	Renesas	Differential-to-LVDS Fanout Buffer • Four differential LVDS output pairs • Selectable differential CLK/nCLK or LVPECL clock inputs • CLK/nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • PCLK/nPCLK pair can accept the following differenti
17	ICS854104	Renesas	Differential-to-LVDS Fanout Buffer • Four differential LVDS output pairs • One differential clock input pair • CLK/nCLK can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • Each output has an individual OE control • Maximum output frequency: 700MHz •
18	ICS8305I	Renesas	LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER • 4 LVCMOS/LVTTL outputs • Selectable differential or LVCMOS/LVTTL clock inputs • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • LVCMOS_CLK supports the following input types: LVCMOS, LVTTL • Max
19	ICS8305	Renesas	LVCMOS-to-LVCMOS/LVTTL Fanout Buffer • Four LVCMOS / LVTTL outputs, 7 output impedance • Selectable differential or LVCMOS / LVTTL clock inputs • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • LVCMOS_CLK supports the following inpu
20	ICS8432-101	Renesas	DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER • Dual differential 3.3V LVPECL outputs • Selectable CLK, nCLK or LVCMOS/LVTTL TEST_CLK • TEST_CLK can accept the following input levels: LVCMOS or LVTTL • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL,