No. | parte # | Fabricante | Descripción | Hoja de Datos |
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Renesas |
FemtoClock Clock Generator ▪ Low power, less than 1.4W typical ▪ Low jitter, less than 100 fs-RMS ▪ PCIe Gen 1-6 CC, SRIS, and SRNS support ▪ Up to six fractional output dividers and 12 integer output dividers • Each fractional output divider is free-run and locked to APLL ▪ E |
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Renesas |
Octal Buffers / Line Drivers • VCC = 1.65 to 5.5 V • All inputs VIH (Max) = 5.5 V (@VCC = 0 to 5.5 V) • All outputs VO (Max) = 5.5 V (@VCC = 0 V or output off state) • Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C) • Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta |
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Renesas |
Dual Monostable Multivibrators both a negative, A, and a positive, B, transition triggered input, either of which can be used as an inhibit. Also included is a clear input that when taken low resets the one shot. The HD74HC221 can be triggered on the positive transition of the cle |
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Renesas |
Silicon Schottky Barrier Diode • Low reverse current, Low capacitance. • Ultra small Flat Lead Package (UFP) is suitable for surface mount design. Ordering Information Type No. HSC226 Cathode Mark S4 Package Name UFP Package Code PWSF0002ZA-A Pin Arrangement Cathode mark Mark 1 |
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Renesas |
2SC2223 |
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Renesas |
Sub-100fs Frequency Synthesizer • Jitter as low as 64 fs RMS maximum (10Hz to 20MHz) • PLL core consists of fractional-feedback Analog PLL (APLL) ○ Operates from a 25MHz to 80MHz crystal or XO ○ APLL frequency independent of input / crystal frequency ○ Operates as a frequency synth |
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