Renesas 8S8 Hoja de datos

No.	parte #	Fabricante	Descripción
1	8S89832I	Renesas	1-to-4 Differential-to-LVDS Fanout Buffer • Four differential LVDS output pairs • IN, nIN input pairs can accept the following differential input levels: LVPECL, LVDS, SSTL • 50 internal input termination to VT • Maximum output frequency: 2GHz • Output skew: 25ps (maximum) • Part-to-part sk
2	8S89831I	Renesas	Differential LVPECL-To-LVPECL/ECL Fanout Buffer • Four LVPECL/ECL outputs • IN, nIN input can accept the following differential input levels: LVPECL, LVDS, CML, SSTL • 50 internal input termination to VT • Output frequency: >2.1GHz • Output skew: 30ps (maximum) • Part-to-part skew: 185ps (maximum
3	8S89833	Renesas	1-To-4 Differential-To-LVDS Fanout Buffer w/Internal Termination • Four differential LVDS outputs • IN, nIN input pair can accept the following differential input levels: LVPECL, LVDS, CML • Output frequency: 2GHz • Cycle-to-cycle jitter, RMS: 3.5ps (maximum) • Additive phase jitter, RMS: 0.03ps (typical) • Output
4	8S89834I	Renesas	2-to-4 LVCMOS/LVTTL-toLVPECL/ECL Clock Multiplexer • Four differential LVPECL/ECL output pairs • Two LVCMOS/LVTTL clock inputs • Maximum output frequency: 1GHz • Output skew: 30ps (maximum) • Part-to-part skew: 100ps (maximum) • Propagation delay: 550ps (maximum) • Additive phase jitter, RMS: 0.12ps
5	8S89296	Renesas	LVDS Programmable Delay Line ▪ One LVDS level output ▪ One differential clock input pair ▪ Differential input clock (IN, nIN) can accept the following signaling levels: LVPECL, LVDS, CML ▪ Maximum frequency: 800MHz ▪ Programmable Delay Range: 2.2ns to 12.5ns in 10ps steps ▪ D[10