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LVCMOS / LVTTL Fanout Buffer a pair of LVCMOS/ LVTTL outputs. The 8302 is characterized at full 3.3V for input VDD,and mixed 3.3V and 2.5V for output operating supply modes (VDDO). Guaranteed output and part-to-part skew characteristics make the 8302 ideal for clock distribution |
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Differential-to-LVCMOS/LVTTL Fanout Buffer • Two LVCMOS/LVTTL outputs • Differential CLK/nCLK input pair • CLK/nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Output frequency: 350MHz (typical) • Output skew: 20ps (maximum) • Part-to-part skew: |
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RS-485/RS-422 Transceivers • Pb-Free Available (RoHS Compliant) • RS-485 I/O Pin ESD Protection . . . . . . . . . . ±15kV HBM Class 3 ESD Protection (HBM) on all Pins. . . . . . . . >7kV • Tiny MSOP Packages Save 50% Board Space • Full Fail-Safe (Open, Short, Terminated and Fl |
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Single-Ended Multiplexer • 2:1 single-ended multiplexer • Q nominal output impedance: 15Ω (V = 3.3V) DDO • Maximum output frequency: 250MHz • Propagation delay: 2.7ns (maximum), (V = V = 3.3V) DD DDO • Input skew: 160ps (maximum), (V = V = 3.3V) DD DDO • Part-to-par |
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Single-Ended Multiplexer • 8:1 single-ended multiplexer • Q nominal output impedance: 7Ω (V = 3.3V) DDO • Maximum output frequency: 250MHz • Propagation delay: 3ns (maximum), V = V = 3.3V DD DDO • Input skew: 225ps (maximum), V = V = 3.3V DD DDO • Part-to-part skew: |
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LVCMOS-to-LVCMOS Fanout Buffer • Four LVCMOS/LVTTL outputs, (two banks of two LVCMOS outputs) • Selectable differential CLK, nCLK pair or LVCMOS_CLK input • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL • LVCMOS_CLK supports the foll |
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RS-485/RS-422 Transceivers • Pb-Free Available (RoHS Compliant) • RS-485 I/O Pin ESD Protection . . . . . . . . . . ±15kV HBM Class 3 ESD Protection (HBM) on all Pins. . . . . . . . >7kV • Tiny MSOP Packages Save 50% Board Space • Full Fail-Safe (Open, Short, Terminated and Fl |
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RS-485/RS-422 Transceivers • Pb-Free Available (RoHS Compliant) • RS-485 I/O Pin ESD Protection . . . . . . . . . . ±15kV HBM Class 3 ESD Protection (HBM) on all Pins. . . . . . . . >7kV • Tiny MSOP Packages Save 50% Board Space • Full Fail-Safe (Open, Short, Terminated and Fl |
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RS-485/RS-422 Transceivers • Pb-Free Available (RoHS Compliant) • RS-485 I/O Pin ESD Protection . . . . . . . . . . ±15kV HBM Class 3 ESD Protection (HBM) on all Pins. . . . . . . . >7kV • Tiny MSOP Packages Save 50% Board Space • Full Fail-Safe (Open, Short, Terminated and Fl |
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Differential-to-LVCMOS Translator/Buffer • Two LVCMOS / LVTTL outputs • Two differential CLKx, nCLKx input pairs • CLK, nCLK pairs can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL • Maximum output frequency: 350MHz (typical) • Output skew: 60ps (maximum) |
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NG Crystal-to-HCSL Frequency Synthesizer • Fourth generation FemtoClock® Next Generation (NG) technology • Three differential HCSL outputs, one differential LVPECL and two single-ended LVCMOS/LVTTL outputs • Crystal oscillator interface designed for a 25MHz, 12pF parallel resonant crystal • |
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Single-Ended Multiplexer • 4:1 single-ended multiplexer • Q nominal output impedance: 7Ω (V = 3.3V) DDO • Maximum output frequency: 250MHz • Propagation delay: 3ns (maximum), V = V = 3.3V DD DDO • Input skew: 225ps (maximum), V = V = 3.3V DD DDO • Part-to-part skew: |
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LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER • 4 LVCMOS/LVTTL outputs • Selectable differential or LVCMOS/LVTTL clock inputs • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • LVCMOS_CLK supports the following input types: LVCMOS, LVTTL • Max |
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Single-Ended Multiplexer • 8:1 single-ended multiplexer • Q nominal output impedance: 7Ω (V = 3.3V) DDO • Maximum output frequency: 250MHz • Propagation delay: 3ns (maximum), V = V = 3.3V DD DDO • Input skew: 225ps (maximum), V = V = 3.3V DD DDO • Part-to-part skew: |
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Single-Ended Multiplexer • 6:1 single-ended multiplexer • Q nominal output impedance: 7Ω (V = 3.3V) DDO • Maximum output frequency: 250MHz • Propagation delay: 3ns (maximum), V = V = 3.3V DD DDO • Input skew: 225ps (maximum), V = V = 3.3V DD DDO • Part-to-part skew: |
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Single-Ended Multiplexer • Four-bit, 2:1 single-ended multiplexer • Nominal output impedance: 15Ω (V = 3.3V) DDO • Maximum output frequency: 250MHz • Propagation delay: 3.2ns (maximum), V = V = 3.3V DD DDO • Input skew: 170ps (maximum), V = V = 3.3V DD DDO • Output |
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Single-Ended Multiplexer • 2-bit, 2:1 single-ended multiplexer • Nominal output impedance: 15 (VDDO = 3.3V) • Maximum output frequency: 250MHz • Propagation delay: 3ns (maximum), VDD = VDDO = 3.3V • Input skew: 85ps (maximum), VDD = VDDO = 3.3V • Part-to-part skew: 500ps (m |
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1-to-2 Differential-to-LVCMOS/LVTTL Fanout Buffer • Two LVCMOS / LVTTL outputs • Differential CLK, nCLK input pair • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • Maximum output frequency: 350MHz • Output skew: 15ps (maximum) • Part-to-part ske |
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1-bit to 2-bit Address Driver • VCC = 2.3 V to 3.6 V • Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C) • Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C) • High output current ±12 mA (@VCC = 3.0 V) • Bus hold on data inputs eliminates the need for external pul |
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RS-485/RS-422 Transceivers • Pb-Free Available (RoHS Compliant) • RS-485 I/O Pin ESD Protection . . . . . . . . . . ±15kV HBM Class 3 ESD Protection (HBM) on all Pins. . . . . . . . >7kV • Tiny MSOP Packages Save 50% Board Space • Full Fail-Safe (Open, Short, Terminated and Fl |
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Desde 2024. D4U Semiconductor.
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