Qimonda HYS Hoja de datos

No.	parte #	Fabricante	Descripción
1	HYS72T256220HP3-B	Qimonda AG	240-Pin Registered DDR2 SDRAM Modules • • • • • • • • • • Programmable self refresh rate via EMRS2 setting Programmable partial array refresh via EMRS2 settings DCC enabling via EMRS2 setting All inputs and outputs SSTL_18 compatible Off-Chip Driver Impedance Adjustment (OCD) and On-Die
2	HYS72T256023HR-5-A	Qimonda	240-Pin Registered DDR2 SDRAM Modules • Auto Refresh (CBR) and Self Refresh • Average Refresh Period 7.8 µs at a TCASE lower than 85 °C, 3.9µs between 85 °C and 95 °C. • All inputs and outputs SSTL_1.8 compatible • Off-Chip Driver Impedance Adjustment (OCD) and On-Die Termination (ODT) •
3	HYS72T512022HR-3.7-A	Qimonda	240-Pin Registered DDR2 SDRAM Modules • Auto Refresh (CBR) and Self Refresh • Average Refresh Period 7.8 µs at a TCASE lower than 85 °C, 3.9µs between 85 °C and 95 °C. • All inputs and outputs SSTL_1.8 compatible • Off-Chip Driver Impedance Adjustment (OCD) and On-Die Termination (ODT) •
4	HYS64T64020HU	Qimonda AG	240-Pin Unbuffered DDR2 SDRAM Modules for average self refresh and self refresh rate to Feature list Chapter 3 Chapter 3 Chapter 4 Chapter 4 Chapter 5 Updated IDD Currents Corrected note 4 - Table 18 Updated SPD Codes SPD Codes update: Byte 49 Bit 0 = 1 (HighT_SRFEntry) for all product t
5	HYS72T64001HP	Qimonda AG	240-Pin Registered DDR2 SDRAM Modules • Programmable CAS Latencies (3, 4 and 5), Burst Length (4 & 8) and Burst Type • Auto Refresh (CBR) and Self Refresh • Average Refresh Period 7.8 µs at a T lower than 85 °C, 3.9 µs between 85 °C and 95 °C • Programmable self refresh rate via EMRS2 se
6	HYS72T512022EP-3.7-B	Qimonda	240-Pin Dual Die Registered DDR2 SDRAM Modules • • • • • • • • • • Programmable self refresh rate via EMRS2 setting Programmable partial array refresh via EMRS2 settings DCC enabling via EMRS2 setting All inputs and outputs SSTL_18 compatible Off-Chip Driver Impedance Adjustment (OCD) and On-Die
7	HYS72T512122HFN-3.7-A	Qimonda	240-Pin Fully-Buffered DDR2 SDRAM Modules DDR2 SDRAM • Detects errors on the channel and reports them to the host memory controller. • Automatic DDR2 DRAM Bus Calibration. • Automatic Channel Calibration. • Full Host Control of the DDR2 DRAMs. • Over-Temperature Detection and Alert. • Hot Add-on and Ho
8	HYS72T512341HKP-3.7-B	Qimonda	240-Pin Registered DDR2 SDRAM Modules • • • • • • • • • Programmable self refresh rate via EMRS2 setting Programmable partial array refresh via EMRS2 settings DCC enabling via EMRS2 setting All inputs and outputs SSTL_18 compatible Off-Chip Driver Impedance Adjustment (OCD) and On-Die Te
9	HYS64T256020EDL-25F-C	Qimonda AG	200-Pin SO-DIMM DDR2 SDRAM Modules • • • • • • • • • • Auto Refresh for temperatures above 85 °C tREFI = 3.9 µs. Programmable self refresh rate via EMRS2 setting. Programmable partial array refresh via EMRS2 settings. DCC enabling via EMRS2 setting. All inputs and outputs SSTL_1.8 com
10	HYS64T256020EDL-3S-C	Qimonda AG	200-Pin SO-DIMM DDR2 SDRAM Modules • • • • • • • • • • Auto Refresh for temperatures above 85 °C tREFI = 3.9 µs. Programmable self refresh rate via EMRS2 setting. Programmable partial array refresh via EMRS2 settings. DCC enabling via EMRS2 setting. All inputs and outputs SSTL_1.8 com
11	HYS64T256020EDL-3.7-C	Qimonda AG	200-Pin SO-DIMM DDR2 SDRAM Modules • • • • • • • • • • Auto Refresh for temperatures above 85 °C tREFI = 3.9 µs. Programmable self refresh rate via EMRS2 setting. Programmable partial array refresh via EMRS2 settings. DCC enabling via EMRS2 setting. All inputs and outputs SSTL_1.8 com
12	HYS64T256022EDL-3-B	Qimonda AG	200-Pin Dual Die Small-Outline-DDR2-SDRAM Modules • Programmable self refresh rate via EMRS2 setting • Programmable partial array refresh via EMRS2 settings • Average Refresh Period 7.8 µs at a TCASE lower than 85°C, 3.9µs between 85°C and 95°C. • DCC enabling via EMRS2 setting • All inputs and outp
13	HYS72T256220HP2.5-B	Qimonda AG	240-Pin Registered DDR2 SDRAM Modules • • • • • • • • • • Programmable self refresh rate via EMRS2 setting Programmable partial array refresh via EMRS2 settings DCC enabling via EMRS2 setting All inputs and outputs SSTL_18 compatible Off-Chip Driver Impedance Adjustment (OCD) and On-Die
14	HYS72T128000HP3.7-B	Qimonda AG	240-Pin Registered DDR2 SDRAM Modules • • • • • • • • • • Programmable self refresh rate via EMRS2 setting Programmable partial array refresh via EMRS2 settings DCC enabling via EMRS2 setting All inputs and outputs SSTL_18 compatible Off-Chip Driver Impedance Adjustment (OCD) and On-Die
15	HYS72T64301HP-3.7-A	Qimonda	240-Pin Registered DDR2 SDRAM Modules • Programmable CAS Latencies (3, 4 and 5), Burst Length (4 & 8) and Burst Type • Auto Refresh (CBR) and Self Refresh • Average Refresh Period 7.8 µs at a TCASE lower than 85°C, 3.9 µs between 85 °C and 95 °C • Programmable self refresh rate via EMRS2
16	HYS72T25620HFD-3S-B	Qimonda AG	240-Pin Fully-Buffered DDR2 SDRAM Modules • Detects errors on the channel and reports them to the host memory controller. • Automatic DDR2 DRAM Bus Calibration. • Automatic Channel Calibration. • Full Host Control of the DDR2 DRAMs. • Over-Temperature Detection and Alert. • Hot Add-on and Ho
17	HYS64T64000	Qimonda	(HYSxxTxxxxx0) 240-Pin Unbuffered DDR2 SDRAM Modules • • • • • • • • • • Auto Refresh (CBR) and Self Refresh Programmable self refresh rate via EMRS2 setting Programmable partial array refresh via EMRS2 settings DCC enabling via EMRS2 setting All inputs and outputs SSTL_1.8 compatible Off-Chip Driver I
18	HYS72T512022HR-3S-A	Qimonda	240-Pin Registered DDR2 SDRAM Modules • Auto Refresh (CBR) and Self Refresh • Average Refresh Period 7.8 µs at a TCASE lower than 85 °C, 3.9µs between 85 °C and 95 °C. • All inputs and outputs SSTL_1.8 compatible • Off-Chip Driver Impedance Adjustment (OCD) and On-Die Termination (ODT) •
19	HYS72T512022HR-5-A	Qimonda	240-Pin Registered DDR2 SDRAM Modules • Auto Refresh (CBR) and Self Refresh • Average Refresh Period 7.8 µs at a TCASE lower than 85 °C, 3.9µs between 85 °C and 95 °C. • All inputs and outputs SSTL_1.8 compatible • Off-Chip Driver Impedance Adjustment (OCD) and On-Die Termination (ODT) •
20	HYS72T512341HJP-3.7-B	Qimonda	240-Pin Registered DDR2 SDRAM Modules • • • • • • • • • Programmable self refresh rate via EMRS2 setting Programmable partial array refresh via EMRS2 settings DCC enabling via EMRS2 setting All inputs and outputs SSTL_18 compatible Off-Chip Driver Impedance Adjustment (OCD) and On-Die Te