No. | parte # | Fabricante | Descripción | Hoja de Datos |
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Qimonda AG |
240-Pin Registered DDR2 SDRAM Modules • • • • • • • • • • Programmable self refresh rate via EMRS2 setting Programmable partial array refresh via EMRS2 settings DCC enabling via EMRS2 setting All inputs and outputs SSTL_18 compatible Off-Chip Driver Impedance Adjustment (OCD) and On-Die |
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Qimonda AG |
240-Pin Unbuffered DDR2 SDRAM Modules for average self refresh and self refresh rate to Feature list Chapter 3 Chapter 3 Chapter 4 Chapter 4 Chapter 5 Updated IDD Currents Corrected note 4 - Table 18 Updated SPD Codes SPD Codes update: Byte 49 Bit 0 = 1 (HighT_SRFEntry) for all product t |
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Qimonda AG |
240-Pin Registered DDR2 SDRAM Modules • Programmable CAS Latencies (3, 4 and 5), Burst Length (4 & 8) and Burst Type • Auto Refresh (CBR) and Self Refresh • Average Refresh Period 7.8 µs at a T lower than 85 °C, 3.9 µs between 85 °C and 95 °C • Programmable self refresh rate via EMRS2 se |
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Qimonda AG |
200-Pin SO-DIMM DDR2 SDRAM Modules • • • • • • • • • • Auto Refresh for temperatures above 85 °C tREFI = 3.9 µs. Programmable self refresh rate via EMRS2 setting. Programmable partial array refresh via EMRS2 settings. DCC enabling via EMRS2 setting. All inputs and outputs SSTL_1.8 com |
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Qimonda AG |
200-Pin SO-DIMM DDR2 SDRAM Modules • • • • • • • • • • Auto Refresh for temperatures above 85 °C tREFI = 3.9 µs. Programmable self refresh rate via EMRS2 setting. Programmable partial array refresh via EMRS2 settings. DCC enabling via EMRS2 setting. All inputs and outputs SSTL_1.8 com |
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Qimonda AG |
200-Pin SO-DIMM DDR2 SDRAM Modules • • • • • • • • • • Auto Refresh for temperatures above 85 °C tREFI = 3.9 µs. Programmable self refresh rate via EMRS2 setting. Programmable partial array refresh via EMRS2 settings. DCC enabling via EMRS2 setting. All inputs and outputs SSTL_1.8 com |
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Qimonda AG |
200-Pin Dual Die Small-Outline-DDR2-SDRAM Modules • Programmable self refresh rate via EMRS2 setting • Programmable partial array refresh via EMRS2 settings • Average Refresh Period 7.8 µs at a TCASE lower than 85°C, 3.9µs between 85°C and 95°C. • DCC enabling via EMRS2 setting • All inputs and outp |
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Qimonda AG |
240-Pin Registered DDR2 SDRAM Modules • • • • • • • • • • Programmable self refresh rate via EMRS2 setting Programmable partial array refresh via EMRS2 settings DCC enabling via EMRS2 setting All inputs and outputs SSTL_18 compatible Off-Chip Driver Impedance Adjustment (OCD) and On-Die |
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Qimonda AG |
240-Pin Registered DDR2 SDRAM Modules • • • • • • • • • • Programmable self refresh rate via EMRS2 setting Programmable partial array refresh via EMRS2 settings DCC enabling via EMRS2 setting All inputs and outputs SSTL_18 compatible Off-Chip Driver Impedance Adjustment (OCD) and On-Die |
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Qimonda AG |
240-Pin Fully-Buffered DDR2 SDRAM Modules • Detects errors on the channel and reports them to the host memory controller. • Automatic DDR2 DRAM Bus Calibration. • Automatic Channel Calibration. • Full Host Control of the DDR2 DRAMs. • Over-Temperature Detection and Alert. • Hot Add-on and Ho |
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Qimonda AG |
200-Pin SO-DIMM DDR2 SDRAM Modules • • • • • • • • • • Auto Refresh for temperatures above 85 °C tREFI = 3.9 µs. Programmable self refresh rate via EMRS2 setting. Programmable partial array refresh via EMRS2 settings. DCC enabling via EMRS2 setting. All inputs and outputs SSTL_1.8 com |
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Qimonda AG |
200-Pin SO-DIMM DDR2 SDRAM Modules • • • • • • • • • • Auto Refresh for temperatures above 85 °C tREFI = 3.9 µs. Programmable self refresh rate via EMRS2 setting. Programmable partial array refresh via EMRS2 settings. DCC enabling via EMRS2 setting. All inputs and outputs SSTL_1.8 com |
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Qimonda AG |
200-Pin Dual Die Small-Outline-DDR2-SDRAM Modules • Programmable self refresh rate via EMRS2 setting • Programmable partial array refresh via EMRS2 settings • Average Refresh Period 7.8 µs at a TCASE lower than 85°C, 3.9µs between 85°C and 95°C. • DCC enabling via EMRS2 setting • All inputs and outp |
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Qimonda AG |
200-Pin Dual Die Small-Outline-DDR2-SDRAM Modules • Programmable self refresh rate via EMRS2 setting • Programmable partial array refresh via EMRS2 settings • Average Refresh Period 7.8 µs at a TCASE lower than 85°C, 3.9µs between 85°C and 95°C. • DCC enabling via EMRS2 setting • All inputs and outp |
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Qimonda AG |
200-Pin Dual Die Small-Outline-DDR2-SDRAM Modules • Programmable self refresh rate via EMRS2 setting • Programmable partial array refresh via EMRS2 settings • Average Refresh Period 7.8 µs at a TCASE lower than 85°C, 3.9µs between 85°C and 95°C. • DCC enabling via EMRS2 setting • All inputs and outp |
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Qimonda AG |
240-Pin Registered DDR2 SDRAM Modules • • • • • • • • • • Programmable self refresh rate via EMRS2 setting Programmable partial array refresh via EMRS2 settings DCC enabling via EMRS2 setting All inputs and outputs SSTL_18 compatible Off-Chip Driver Impedance Adjustment (OCD) and On-Die |
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Qimonda AG |
240-Pin Registered DDR2 SDRAM Modules • • • • • • • • • • Programmable self refresh rate via EMRS2 setting Programmable partial array refresh via EMRS2 settings DCC enabling via EMRS2 setting All inputs and outputs SSTL_18 compatible Off-Chip Driver Impedance Adjustment (OCD) and On-Die |
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Qimonda AG |
240-Pin Registered DDR2 SDRAM Modules • • • • • • • • • • Programmable self refresh rate via EMRS2 setting Programmable partial array refresh via EMRS2 settings DCC enabling via EMRS2 setting All inputs and outputs SSTL_18 compatible Off-Chip Driver Impedance Adjustment (OCD) and On-Die |
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Qimonda AG |
240-Pin Registered DDR2 SDRAM Modules • Programmable CAS Latencies (3, 4 and 5), Burst Length (4 & 8) and Burst Type • Auto Refresh (CBR) and Self Refresh • Average Refresh Period 7.8 µs at a T lower than 85 °C, 3.9 µs between 85 °C and 95 °C • Programmable self refresh rate via EMRS2 se |
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Qimonda AG |
240-Pin Registered DDR2 SDRAM Modules • Programmable CAS Latencies (3, 4, 5 & 6), Burst Length (4 & 8) and Burst Type • Auto Refresh (CBR) and Self Refresh • All inputs and outputs SSTL_18 compatible • Off-Chip Driver Impedance Adjustment (OCD) and On-Die Termination (ODT) • Serial Prese |
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