No. | parte # | Fabricante | Descripción | Hoja de Datos |
---|---|---|---|---|
|
|
Hitachi Semiconductor |
Octal D-type Transparent Latches(with inverted 3-state outputs) • • • • • • LSTTL Output Logic Level Compatibility as well as CMOS Output Compatibility High Speed Operation: tpd (Data to Q) = 14 ns typ (CL = 50 pF) High Output Current: Fanout of 15 LSTTL Loads Wide Operating Voltage: VCC = 4.5 to 5.5 V Low Input |
|
|
|
System Logic Semiconductor |
Dual 2-Bit Transparent Latch = latched data SLS System Logic Semiconductor SL74HC75 MAXIMUM RATINGS * Symbol VCC VIN VOUT IIN IOUT ICC PD Tstg TL * Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC |
|
|
|
Fairchild Semiconductor |
3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops s Choice of 8 latches or 8 D-type flip-flops in a single package s 3-STATE bus-driving outputs s Full parallel-access for loading s Buffered control inputs s P-N-P inputs reduce D-C loading on data lines Ordering Code: Order Number DM74LS373WM DM74L |
|
|
|
Fairchild Semiconductor |
Octal D-Type Transparent Latch with 3-STATE Outputs s Switching specifications at 50 pF s Switching specifications guaranteed over full temperature and VCC range s Advanced oxide-isolated, ion-implanted Schottky TTL process s Functionally and pin for pin compatible with LS and ALS TTL counterparts s I |
|
|
|
National Semiconductor |
16-Bit Transparent Latch n Separate control logic for each byte n 16-bit version of the ABT373 n High impedance glitch free bus loading during entire power up and power down cycle n Non-destructive hot insertion capability n Guaranteed latch-up protection n Standard Microcir |
|
|
|
National Semiconductor |
TRI-STATEE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops Y Y Y Y Y Choice of 8 latches or 8 D-type flip-flops in a single package TRI-STATE bus-driving outputs Full parallel-access for loading Buffered control inputs P-N-P inputs reduce D-C loading on data lines Connection Diagrams Dual-In-Line Packages |
|
|
|
Hitachi Semiconductor |
Octal D-type Transparent Latches any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property |
|
|
|
National Semiconductor |
TRI-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops Y Y Y Y Y Choice of 8 latches or 8 D-type flip-flops in a single package TRI-STATE bus-driving outputs Full parallel-access for loading Buffered control inputs P-N-P inputs reduce D-C loading on data lines Connection Diagrams Dual-In-Line Packages |
|
|
|
Holtek Semiconductor |
BLE Transparent Transmission Module • Operating voltage: 2.2V~3.6V • Operating current: ♦♦ Power down mode: 500nA ♦♦ Sleep mode: 20μA ♦♦ Broadcast mode: 180μA @ 250ms ♦♦ Transparent transmission: 1.1mA @ 20 bytes, 5 times/sec. • Frequency range: 2402MHz~2480MHz • TX output power: |
|
|
|
System Logic Semiconductor |
Octal 3-State Noninverting Transparent Latch(High-Performance Silicon-Gate CMOS) N VOUT IIN IOUT ICC PD Tstg TL * Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Current, per Pin DC Supply Current, VCC and GND Pins Powe |
|
|
|
National Semiconductor |
Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops Y Y Y Y Y Choice of 8 latches or 8 D-type flip-flops in a single package TRI-STATE bus-driving outputs Full parallel-access for loading Buffered control inputs P-N-P inputs reduce D-C loading on data lines Connection Diagrams Dual-In-Line Packages |
|
|
|
ON Semiconductor |
Low-Voltage CMOS Octal Transparent Latch • Designed for 1.2 to 3.6 V VCC Operation • 5 V Tolerant − Interface Capability With 5 V TTL Logic • Supports Live Insertion and Withdrawal • IOFF Specification Guarantees High Impedance When VCC = 0 V • 24 mA Output Sink and Source Capability • Near |
|
|
|
ON Semiconductor |
ESD Protection Diode • Protection for the following IEC Standards: IEC61000−4−2 Level 4: ±30 kV Contact Discharge IEC61000−4−5 (Lightning) 125 A (8/20 ms) • These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant MAXIMUM RATINGS Rating Symbol Value U |
|
|
|
Fairchild Semiconductor |
Low Voltage 16-Bit Transparent Latch |
|
|
|
Hitachi Semiconductor |
Octal D-type Transparent Latches(with inverted 3-state outputs) • • • • • • LSTTL Output Logic Level Compatibility as well as CMOS Output Compatibility High Speed Operation: tpd (Data to Q) = 14 ns typ (CL = 50 pF) High Output Current: Fanout of 15 LSTTL Loads Wide Operating Voltage: VCC = 4.5 to 5.5 V Low Input |
|
|
|
Hitachi Semiconductor |
Octal Transparent Latches (with 3-state outputs) • • • • • • LSTTL Output Logic Level Compatibility as well as CMOS Output Compatibility High Speed Operation: tpd (D to Q, Q) = 13 ns typ (CL = 50 pF) High Output Current: Fanout of 15 LSTTL Loads Wide Operating Voltage: VCC = 4.5 to 5.5 V Low Input |
|
|
|
Hitachi Semiconductor |
Octal D-type Transparent Latches any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property |
|
|
|
Fairchild Semiconductor |
Low Voltage 16-Bit Transparent Latch s 1.65V to 3.6V VCC supply operation s 3.6V tolerant control inputs and outputs s Bushold on data inputs eliminates the need for external pull-up/pull-down resistors s 26Ω series resistors in outputs s tPD (In to On) 3.8 ns max for 3.0V to 3.6V VCC 5 |
|
|
|
Fairchild Semiconductor |
Octal Transparent Latch s ICC and IOZ reduced by 50% s Eight latches in a single package s 3-STATE outputs for bus interfacing s Outputs source/sink 24 mA s ACT373 has TTL-compatible inputs Ordering Code: Order Number 74AC373SC 74AC373SJ 74AC373MTC 74AC373PC 74ACT373SC 74A |
|
|
|
Fairchild Semiconductor |
3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops |
|