| No. | parte # | Fabricante | Descripción | Hoja de Datos |
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ON Semiconductor |
LVTTL/LVCOMS to Differential LVECL Translator • 350 ps Typical Propagation Delay • Maximum Input Clock Frequency = > 1.0 GHz Typical • The 100 Series Contains Temperature Compensation • Operating Range: VCC = 3.0 V to 3.6 V; VEE = −3.6 V to −3.0 V; GND = 0 V • PNP LVTTL Input for Minimal Loading |
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ON Semiconductor |
4-Bit Dual-Supply Non-Inverting Level Translator • Wide VCCA and VCCB Operating Range: 0.9 V to 4.5 V • High−Speed w/ Balanced Propagation Delay • Inputs and Outputs have OVT Protection to 4.5 V • Non−preferential VCCA and VCCB Sequencing • Outputs at 3−State until Active VCC is Reached • Power−Off |
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Union Semiconductor |
Dual bidirectional I2C-bus and SMBus voltage-level translator z 2-Bit Bidirectional Translator for SDA z Open-Drain I2C-Bus I/O Ports (SCL1, and SCL Lines in Mixed-Mode I2C-Bus SDA1, SCL2 and SDA2) Applications z Provides Bidirectional Voltage z Standard-Mode, Fast-Mode, Fast-Mode Translation with no D |
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ON Semiconductor |
3.3 V Quad LVCMOS Differential Line Receiver Translator • Accepts M−LVDS, LVDS, LVPECL and HCSL Differential Input Signal Levels • Maximum Data Rate of 400 Mbps • Maximum Clock Frequency of 200 MHz • 25 ps Typical Channel−to−Channel Skew • 3.3 ns Maximum Propagation Delay • 3.3 V ±10% Power Supply • High |
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ON Semiconductor |
Registered Hex TTL/ECL Translator differential ECL outputs as well as a choice between either a differential ECL clock input or a TTL clock input. The asynchronous master reset control is an ECL level input. With its differential ECL outputs and TTL inputs the H604 device is ideally |
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Micrel Semiconductor |
DUAL TTL-to-DIFFERENTIAL PECL TRANSLATOR ■ ■ ■ ■ ■ ■ 300ps typical propagation delay <100ps output-to-output skew Differential PECL outputs PNP TTL inputs for minimal loading Flow-through pinouts Available in 8-pin SOIC package DESCRIPTION The SY10/100ELT22 are dual TTL-to-differential PEC |
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NXP Semiconductors |
Dual supply translating transceiver two 4-bit input-output ports (An and Bn), one output enable input (OE) and two supply pins (VCC(A) and VCC(B)). VCC(A) can be supplied at any voltage between 1.65 V and 3.6 V and VCC(B) can be supplied at any voltage between 2.3 V and 5.5 V, making t |
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NXP Semiconductors |
Low-voltage translating 16-bit I2C-bus/SMBus I/O expander specifically designed to enhance the I/ O. These additional features are: programmable output drive strength, latchable inputs, programmable pull-up/pull-down resistors, maskable interrupt, interrupt status register, programmable open-drain or push-p |
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Fairchild Semiconductor |
2-Bit Voltage Translator / Isolator Bi-Directional Interface between Any Two Levels: 1.65V to 5.5V No Direction Control Needed Internal 10K Pull-Up Resistors System GPIO Resources Not Required when OE Tied to VCCA I2C-Bus® Isolation A/B Port VOL = 175mV (Typical), VIL = 150 |
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ON Semiconductor |
1-Bit Dual-Supply Inverting Level Translator • Wide VCCA and VCCB Operating Range: 0.9 V to 4.5 V • High−Speed w/ Balanced Propagation Delay • Inputs and Outputs have OVT Protection to 4.5 V • Non−preferential VCCA and VCCB Sequencing • Outputs at 3−State until Active VCC is Reached • Power−Off |
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ON Semiconductor |
Level-Translating I2C-Bus Repeater • 2 Channel, Bidirectional Buffer Isolates Capacitance and Allows 400 pF on Either Side of the Device • Voltage Level Translation from 0.9 V to 5.5 V and from 2.7 V to 5.5 V • Footprint and Functional Replacement for PCA9515/15A • I2C−bus and SMBus C |
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Fairchild Semiconductor |
Low Voltage IEEE 161284 Translating Transceiver s Supports IEEE 1284 Level 1 and Level 2 signaling standards for bidirectional parallel communications between personal computers and printing peripherals s Translation capability allows outputs on the cable side to interface with 5V signals s All in |
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Fairchild Semiconductor |
Low Voltage IEEE 161284 Translating Transceiver s Supports IEEE 1284 Level 1 and Level 2 signaling standards for bidirectional parallel communications between personal computers and printing peripherals with the exception of output slew rate s Translation capability allows outputs on the cable sid |
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National Semiconductor |
Dual Voltage Level Translator Y 31 volt (max) output swing Y 1 mW power dissipation in normal state Y Standard 5V power supply Y Temperature range DS7800 DS8800 b55 C to a125 C 0 C to a70 C Y Compatible with all MOS devices Schematic and Connection Diagrams Metal Can Pack |
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Union Semiconductor |
4-Bit Bidirectional Voltage-Level Translator z Low-Voltage ASIC Level Translation z Cell-Phone Cradles z Portable POS Systems z Portable Communication Devices z Low-Cost Serial Interfaces z Cell-Phones z GPS z Telecommunications Equipment z 1.2V to 3.6V on A Port and 1.65V to 5.5V on B Port ( |
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Union Semiconductor |
2-Bit Bidirectional Voltage-Level Translator z Low-Voltage ASIC Level Translation z Cell-Phone Cradles z Portable POS Systems z Portable Communication Devices z Low-Cost Serial Interfaces z Cell-Phones z GPS z Telecommunications Equipment z 1.2V to 3.6V on A Port and 1.65V to 5.5V on B Port ( |
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Union Semiconductor |
Bidirectional Voltage Level Translator z SPI, MICROWIRE, and I2C Level z Provides Bidirectional Voltage Translation Translation z Low-Voltage ASIC Level Translation z Smart Card Readers z Cell-phone Cradles z Portable POS Systems z Portable Communication Devices z Low-Cost Serial Interf |
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Union Semiconductor |
2-Bit Bidirectional Voltage Level Translator z I2C, SMBus and SPI Level Translation z Less than 3.5ns Maximum Propagation z Low-Voltage ASIC Level Translation Delay to Accommodate Standard-Mode and z Smart Card Readers Fast-Mode I2C-Bus Devices and Multiple z Cell-Phone Cradles Masters |
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National Semiconductor |
Dual Voltage Translator The DM7800/DM8800 are dual voltage translators designed for interfacing between conventional TTL or DTL voltage levels and those levels associated with high impedance junction or MOS FET-type devices_ The design allows the user a wide latitude in hi |
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ON Semiconductor |
9-Bit TTL/ECL Translator both ECL and TTL logic enable controls for maximum flexibility. The 10H version is compatible with MECL 10H ECL logic levels. The 100H version is compatible with 100K levels. Features http://onsemi.com • 9−Bit Ideal for Byte−Parity Applications • F |
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Desde 2024. D4U Semiconductor.
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