| No. | parte # | Fabricante | Descripción | Hoja de Datos |
|---|---|---|---|---|
|
|
|
ON Semiconductor |
Single Non-Inverting Buffer • Designed for 2.0 V to 5.5 V VCC Operation • 3.5 ns tPD at 5 V (typ) • Inputs/Outputs Over−Voltage Tolerant up to 5.5 V • IOFF Supports Partial Power Down Protection • Source/Sink 8 mA at 3.0 V • Available in SC−88A and TSOP−5 Packages • Chip Comple |
|
|
|
|
ON Semiconductor |
Single Non-Inverting Buffer • Designed for 2.0 V to 5.5 V VCC Operation • 3.5 ns tPD at 5 V (typ) • Inputs/Outputs Over−Voltage Tolerant up to 5.5 V • IOFF Supports Partial Power Down Protection • Source/Sink 8 mA at 3.0 V • Available in SC−88A and TSOP−5 Packages • Chip Comple |
|
|
|
|
ON Semiconductor |
Buffer • Designed for 2.0 V to 5.5 V VCC Operation • 3.5 ns tPD at 5 V (typ) • Inputs/Outputs Over−Voltage Tolerant up to 5.5 V • IOFF Supports Partial Power Down Protection • Source/Sink 8 mA at 3.0 V • Available in SC−88A, TSOP−5, SOT−953 and UDFN6 Packag |
|
|
|
|
ON Semiconductor |
Single 2-Input NOR Gate • High Speed: tPD = 7 ns (Typ) at VCC = 5 V • Low Power Dissipation: ICC = 1 mA (Max) at TA = 25°C • High Noise Immunity • Balanced Propagation Delays (tpLH = tpHL) • Symmetrical Output Impedance (IOH = IOL = 2 mA) • Chip Complexity: < 100 FETs • NLV |
|
|
|
|
ON Semiconductor |
2-Input NAND Schmitt-Trigger • Designed for 2.0 V to 5.5 V VCC Operation • 4.9 ns tPD at 5 V (typ) • Inputs/Outputs Over−Voltage Tolerant up to 5.5 V • IOFF Supports Partial Power Down Protection • Source/Sink 8 mA at 3.0 V • Available in SC−88A and TSOP−5 Packages • Chip Comple |
|
|
|
|
ON Semiconductor |
Single 2-Input NOR Gate • Designed for 2.0 V to 5.5 V VCC Operation • 3.5 ns tPD at 5 V (typ) • Inputs/Outputs Over−Voltage Tolerant up to 5.5 V • IOFF Supports Partial Power Down Protection • Source/Sink 8 mA at 3.0 V • Available in SC−88A, TSOP−5 and SOT−953 Packages • Ch |
|
|
|
|
ON Semiconductor |
Single Inverter |
|
|
|
|
ON Semiconductor |
Single 2-Input Exclusive OR Gate • Designed for 2.0 V to 5.5 V VCC Operation • 3.5 ns tPD at 5 V (typ) • Inputs/Outputs Over−Voltage Tolerant up to 5.5 V • IOFF Supports Partial Power Down Protection • Source/Sink 8 mA at 3.0 V • Available in SC−88A and TSOP−5 Packages • Chip Comple |
|
|
|
|
ON Semiconductor |
Single 2-Input NOR Gate • Designed for 2.0 V to 5.5 V VCC Operation • 3.5 ns tPD at 5 V (typ) • Inputs/Outputs Over−Voltage Tolerant up to 5.5 V • IOFF Supports Partial Power Down Protection • Source/Sink 8 mA at 3.0 V • Available in SC−88A and TSOP−5 Packages • Chip Comple |
|
|
|
|
ON Semiconductor |
Single Inverter • High Speed: tPD = 7 ns (Typ) at VCC = 5 V • Low Power Dissipation: ICC = 1 mA (Max) at TA = 25°C • High Noise Immunity • Balanced Propagation Delays (tpLH = tpHL) • Symmetrical Output Impedance (IOH = IOL = 2 mA) • Chip Complexity: < 100 FETs • NLV |
|
|
|
|
ON Semiconductor |
Single Inverter • Designed for 2.0 V to 5.5 V VCC Operation • 3.5 ns tPD at 5 V (typ) • Inputs/Outputs Over−Voltage Tolerant up to 5.5 V • IOFF Supports Partial Power Down Protection • Source/Sink 8 mA at 3.0 V • Available in SC−88A and TSOP−5 Packages • Chip Comple |
|
|
|
|
ON Semiconductor |
Single 2-Input NOR Gate • Designed for 2.0 V to 5.5 V VCC Operation • 3.5 ns tPD at 5 V (typ) • Inputs/Outputs Over−Voltage Tolerant up to 5.5 V • IOFF Supports Partial Power Down Protection • Source/Sink 8 mA at 3.0 V • Available in SC−88A and TSOP−5 Packages • Chip Comple |
|
|
|
|
ON Semiconductor |
Single Schmitt-Trigger Inverter • Designed for 2.0 V to 5.5 V VCC Operation • 4.0 ns tPD at 5 V (typ) • Inputs/Outputs Over−Voltage Tolerant up to 5.5 V • IOFF Supports Partial Power Down Protection • Source/Sink 8 mA at 3.0 V • Available in SC−88A, TSOP−5 and SOT−953 Packages • Ch |
|
|
|
|
ON Semiconductor |
Configurable Multifunction Gate • Designed for 1.65 V to 5.5 V VCC Operation • 3.3 ns tPD at VCC = 5 V (Typ) • Inputs/Outputs Overvoltage Tolerant up to 5.5 V • IOFF Supports Partial Power Down Protection • Sink 24 mA at 3.0 V • Available in SC−88 Package • Chip Complexity < 100 FE |
|
|
|
|
ON Semiconductor |
Configurable Multifunction Gate • Designed for 1.65 V to 5.5 V VCC Operation • 3.3 ns tPD at VCC = 5 V (Typ) • Inputs/Outputs Overvoltage Tolerant up to 5.5 V • IOFF Supports Partial Power Down Protection • Sink 24 mA at 3.0 V • Available in SC−88 Package • Chip Complexity < 100 FE |
|
|
|
|
ON Semiconductor |
Single 2-Input NAND Gate • Designed for 2.0 V to 5.5 V VCC Operation • 3.5 ns tPD at 5 V (typ) • Inputs/Outputs Over−Voltage Tolerant up to 5.5 V • IOFF Supports Partial Power Down Protection • Source/Sink 8 mA at 3.0 V • Available in SC−88A, TSOP−5, and SOT−953 Packages • C |
|
|
|
|
ON Semiconductor |
Single 2-Input NAND Gate • Designed for 2.0 V to 5.5 V VCC Operation • 3.5 ns tPD at 5 V (typ) • Inputs/Outputs Over−Voltage Tolerant up to 5.5 V • IOFF Supports Partial Power Down Protection • Source/Sink 8 mA at 3.0 V • Available in SC−88A, TSOP−5, and SOT−953 Packages • C |
|
|
|
|
ON Semiconductor |
Single 2-Input AND Gate • Designed for 2.0 V to 5.5 V VCC Operation • 3.5 ns tPD at 5 V (typ) • Inputs/Outputs Over−Voltage Tolerant up to 5.5 V • IOFF Supports Partial Power Down Protection • Source/Sink 8 mA at 3.0 V • Available in SC−88A, TSOP−5 and SOT−953 Packages • Ch |
|
|
|
|
ON Semiconductor |
Single Inverter |
|
|
|
|
ON Semiconductor |
Noninverting 3-State Buffer • Designed for 2.0 V to 5.5 V VCC Operation • 3.5 ns tPD at 5 V (typ) • Inputs/Outputs Over−Voltage Tolerant up to 5.5 V • IOFF Supports Partial Power Down Protection • Source/Sink 8 mA at 3.0 V • Available in SC−88A, TSOP−5 and SOT−953 Packages • Ch |
|
Desde 2024. D4U Semiconductor.
|